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nexys4-ddr:migration_n3 [2015/03/14 05:38] – [EDK Projects] sbobrowicznexys4-ddr:migration_n3 [2022/09/08 15:45] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey
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 ==== ISE Projects ==== ==== ISE Projects ====
  
-This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilentinc.com/|Digilent Forum]].+This can be done by opening the new project in Project Navigator 14.7, and then allowing the tools to automate the update. This typically is successful, but may cause problems when trying to upgrade IP cores if the project is particularly old. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilent.com/|Digilent Forum]].
  
 ==== EDK Projects ==== ==== EDK Projects ====
  
-If your design is an AXI design, Open the Project in Xilinx Platform Studio. Allow the tools to upgrade any IP that it says is safe to upgrade. If the project is too old, it is possible that the version of an IP core you have used is no longer present in 14.7. If this is the case, you may have to upgrade the project to an earlier version that still contains the core before upgrading to 14.7. For example, if your project was created in 13.3, you may need to open it up and upgrade it in 14.2, and then open it again in 14.7. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilentinc.com/|Digilent Forum]].+If your design is an AXI design, Open the Project in Xilinx Platform Studio. Allow the tools to upgrade any IP that it says is safe to upgrade. If the project is too old, it is possible that the version of an IP core you have used is no longer present in 14.7. If this is the case, you may have to upgrade the project to an earlier version that still contains the core before upgrading to 14.7. For example, if your project was created in 13.3, you may need to open it up and upgrade it in 14.2, and then open it again in 14.7. If you run into a problem upgrading your project, try posting the issue on the [[https://forum.digilent.com/|Digilent Forum]].
  
-If your design is a PLB design, then it will need to be redesigned with equivalent AXI versions of the PLB cores. This is because Xilinx does not support the PLB bus in 7-series devices. The easiest way to do this is to start with an AXI project that already has most of the components properly connected, and then to just remove the ones you don't need, and add any additional cores that were in your design. You may use this project for that purpose:+If your design is a PLB design, then it will need to be redesigned with equivalent AXI versions of the PLB cores. This is because Xilinx does not support the PLB bus in 7-series devices. If you still wish to use EDK, then you will need to do this from scratch: we do not have any EDK based reference designs or a base system builder package for the Nexys4-DDR. If you would like to migrate your design to Vivado, many example projects and tutorials are available on the Nexys 4 DDR Resource Center that can help you become acquainted with it. 
  
-FIXME -- Add project 
- 
-That project has the DDR2, ethernet, and nearly all of the other peripherals properly connected to the AXI versions of the cores. Its original purpose was for our Manufacturing test, so the net names may be confusing. If you choose to follow this method, you can skip to step 3. Note you will only need to modify the constraints of any cores you manually add: the constraints that are currently in the project are all correct for the Nexys4-DDR 
  
 ===== Step 2: Target the Nexys4-DDR FPGA ===== ===== Step 2: Target the Nexys4-DDR FPGA =====
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 ==== Instantiated FPGA Resources ==== ==== Instantiated FPGA Resources ====
  
-Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/7series_hdl.pdf|7 Series Libraries Guide.]] +Any instantiated FPGA primitives (DSP slices, PLLs, DDR registers, etc.) will need to be updated to the 7-series equivalent. Note that the usage of these primitives may have changed in order to reflect changes to the 7-series fabric in the Artix part. You will need to consult the Xilinx documentation for the particular feature of the FPGA you are using to see if this is the case. The new primitive declarations are all found in the [[https://www.xilinx.com/htmldocs/xilinx14_7/7series_hdl.pdf|7 Series Libraries Guide.]] 
  
 ==== VHDCI Connector ==== ==== VHDCI Connector ====
  
-The Nexys4-DDR no longer has a high-density/high-speed connector. You will have to remove any aspect of your design that communicates with a device over the VHDCI connector, unless you can modify the device to connect to Pmods instead. +The Nexys4-DDR no longer has a high-density/high-speed connector. You will have to remove any aspect of your design that communicates with a device over the VHDCI connector, unless you can modify the device to connect to Pmods instead. If your design requires a high-density/high-speed connector, you should consider migrating to the [[https://digilent.com/shop/nexys-video-artix-7-fpga-trainer-board-for-multimedia-applications/|NexysVideo]] platform instead, which has a fully populated LPC FMC connector.
 ==== DEPP/DSTM ==== ==== DEPP/DSTM ====
  
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 ===== Still Stuck? ===== ===== Still Stuck? =====
  
-If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https://forum.digilentinc.com/|Digilent Forum]], and we will do are best to get your design up and running.+If you are still having trouble getting your project ported to the Nexys4-DDR, please post your problem on the [[https://forum.digilent.com/|Digilent Forum]], and we will do our best to get your design up and running.