Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
nexys4-ddr:gsg [2015/01/14 23:56] – [Powering it On] sbobrowicznexys4-ddr:gsg [2015/12/10 23:01] (current) – [Working with Vivado] Thomas Kappenman
Line 1: Line 1:
-====== Getting Started with the Nexys4-DDR ======+====== Getting Started with the Nexys4DDR ======
  
 =====What's in the Box?===== =====What's in the Box?=====
Line 5: Line 5:
 ------ ------
 =====Powering it On===== =====Powering it On=====
-To power on the Nexys4-DDR, you will need a micro-USB cable. Plug this cable into the JTAG slot on the Nexys4-DDR, plug the other end into your computer, and flip the power switch to the "On" position. This will begin the out of box demo.+To power on the Nexys4DDR, you will need a micro-USB cable. Plug this cable into the JTAG slot on the Nexys4DDR, plug the other end into your computer, and flip the power switch to the "On" position. This will begin the out of box demo.
  
-More information on this startup demo can be found FIXME.+More information on this startup demo can be found [[nexys4-ddr:userdemo|here]].
 ----- -----
 =====Getting Started with Vivado===== =====Getting Started with Vivado=====
  
-This video will give you step by step instructions to get started with your Nexys4. +The files needed for this demo can be downloaded by clicking {{:nexys4-ddr:abacus_verilog_srcfiles.zip|here}}.  You'll also need the constraints file. The constraint file is dependent on the development environment. For ISE designs the UCF file can be downloaded {{:nexys4-ddr:nexys4ddr_master_ucf.zip|here}}. For Vivado designs, the XDC file can be downloaded {{:nexys4-ddr:nexys4ddr_master_xdc.zip|here}}.
- +
-The files needed for this demo can be downloaded by clicking {{:nexys:nexys4:abacus_verilog_srcfiles.zip|here}}.FIXME  You'll also need the constraints file. The constraint file is dependent on the development environment. For ISE designs the file can be downloaded [[http://digilentinc.com/Data/Products/NEXYS4DDR/Nexys4DDR_Master_ucf.zip|here]]. For Vivado designs, the constraints file can be downloaded [[http://digilentinc.com/Data/Products/NEXYS4DDR/Nexys4DDR_Master_xdc.zip|here]].+
  
 More information on the Abacus project can be found [[basys3:abacus|here]]. More information on the Abacus project can be found [[basys3:abacus|here]].
Line 44: Line 42:
 {{ :basys3:3.png?nolink&500 |}} {{ :basys3:3.png?nolink&500 |}}
  
-This is where we'll import our Xlilinx Design Constraints file (XDC) to map the HDL signals to the Artix-7 pins. Click on "Add Files", navigate to where you saved your [[http://digilentinc.com/Data/Products/NEXYS4/Nexys4_Master_xdc.zip|Nexys4_Master.xdc]] file, select it, and click "Next".+This is where we'll import our Xlilinx Design Constraints file (XDC) to map the HDL signals to the Artix-7 pins. Click on "Add Files", navigate to where you saved your {{:nexys4-ddr:nexys4ddr_master_xdc.zip|Nexys4DDR_Master.xdc}} file, select it, and click "Next".
 {{ :nexys:nexys4:1.png?nolink&500 |}} {{ :nexys:nexys4:1.png?nolink&500 |}}
  
Line 64: Line 62:
  
 ----- -----
- 
 ====Working with Vivado==== ====Working with Vivado====
 FIXME FIXME
Line 75: Line 72:
 {{ :nexys:nexys4:modules2.png?nolink&500 |}} {{ :nexys:nexys4:modules2.png?nolink&500 |}}
  
-Before we run our program, we must first map the signals to pins using the Nexys4_Master.xdc file we imported. To do this, we will open Nexys4_Master.xdc. Inside this file, we will see how Vivado maps signals to pins. Each line should be commented out at this point (with #), so it should look something like this.+Before we run our program, we must first map the signals to pins using the Nexys4DDR_Master.xdc file we imported. To do this, we will open Nexys4DDR_Master.xdc. Inside this file, we will see how Vivado maps signals to pins. Each line should be commented out at this point (with #), so it should look something like this.
  
 {{ :nexys:nexys4:xdcfilecommented.png?nolink&500 |}} {{ :nexys:nexys4:xdcfilecommented.png?nolink&500 |}}
Line 95: Line 92:
 {{ :nexys:nexys4:xdcuncommented.png?nolink&500 |}} {{ :nexys:nexys4:xdcuncommented.png?nolink&500 |}}
  
-After uncommenting the xdc file, save it and we can start programming your Nexys4.+After uncommenting the xdc file, save it and we can start programming your Nexys4DDR.
  
 ----- -----
-====Programming the Nexys4==== +====Programming the Nexys4DDR==== 
-There are two ways to program your Nexys4 FPGA: using a .bit file and using a .bin file. Using a .bit file, we  use the JTAG programming cable to load the bit file into the FPGA. Programming with a .bin file will use the QSPI to program the FPGA each time it is powered on. This means you will not have to reprogram it using the JTAG connector each time. We will specify that we want to generate a .bin file by clicking Tools>Project Settings>Bitstream. In this window we will check the box next to .bin_file.+There are two ways to program your Nexys4DDR FPGA: using a .bit file and using a .bin file. Using a .bit file, we  use the JTAG programming cable to load the bit file into the FPGA. Programming with a .bin file will use the QSPI to program the FPGA each time it is powered on. This means you will not have to reprogram it using the JTAG connector each time. We will specify that we want to generate a .bin file by clicking Tools>Project Settings>Bitstream. In this window we will check the box next to .bin_file.
 {{ :basys3:27.png?nolink&500 |}} {{ :basys3:27.png?nolink&500 |}}
  
Line 109: Line 106:
  
  
-Click "Open Synthesized Design" and then press Ok. You may get several warnings after this, but this just refers to the parts of the Nexys4 master XDC file that weren't implemented by our HDL design. It is good practice to only uncomment signal pins that are being used by the design, but this will not affect us in the end.+Click "Open Synthesized Design" and then press Ok. You may get several warnings after this, but this just refers to the parts of the Nexys4DDR master XDC file that weren't implemented by our HDL design. It is good practice to only uncomment signal pins that are being used by the design, but this will not affect us in the end.
  
 You should now see this window You should now see this window
Line 134: Line 131:
 You will see this screen. You will see this screen.
 {{ :basys3:26.png?nolink&300 |}} {{ :basys3:26.png?nolink&300 |}}
-At this point, make sure your Nexys4 is plugged in via USB and turned on. Now click Next twice and you will see this screen.+At this point, make sure your Nexys4DDR is plugged in via USB and turned on. Now click Next twice and you will see this screen.
 {{ :nexys:nexys4:target.png?nolink&500 |}} {{ :nexys:nexys4:target.png?nolink&500 |}}
 Set the JTAG Clock Frequency to 30000000, select the device, and click "Next" followed by "Finish". Set the JTAG Clock Frequency to 30000000, select the device, and click "Next" followed by "Finish".
  
-===Programming the Nexys4 using a .bit file===+===Programming the Nexys4DDR using a .bit file===
 First, make sure that the jumper JP1 is in the JTAG position. First, make sure that the jumper JP1 is in the JTAG position.
 You should see something like this. You should see something like this.
Line 144: Line 141:
 Click "Program device" (in the green bar) then xc7a35t_0, select your .bit file in the bitstream file box, and click Program. Click "Program device" (in the green bar) then xc7a35t_0, select your .bit file in the bitstream file box, and click Program.
 {{ :nexys:nexys4:programdevice.png?nolink&500 |}} {{ :nexys:nexys4:programdevice.png?nolink&500 |}}
-This will program your Nexys4 through the JTAG connector.+This will program your Nexys4DDR through the JTAG connector.
  
-===Programming the Nexys4 using .bin file===+===Programming the Nexys4DDR using .bin file===
 First, make sure the jumper on JP1 is in the QSPI position First, make sure the jumper on JP1 is in the QSPI position
 In the Hardware Manager window, under hardware right click your device and click Add Configuration Memory Device... In the Hardware Manager window, under hardware right click your device and click Add Configuration Memory Device...
Line 156: Line 153:
 {{ :nexys:nexys4:program_config.png?nolink&500 |}} {{ :nexys:nexys4:program_config.png?nolink&500 |}}
  
-Vivado will now erase the old configuration file, and reprogram your Nexys4 with the Abacus demo file. From now on, when you power cycle the Nexys4, the abacus demo will load at startup.+Vivado will now erase the old configuration file, and reprogram your Nexys4DDR with the Abacus demo file. From now on, when you power cycle the Nexys4DDR, the abacus demo will load at startup.