Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
learn:programmable-logic:tutorials:use-flip-flops-to-build-a-clock-divider:start [2016/07/22 19:46] – Marthalearn:programmable-logic:tutorials:use-flip-flops-to-build-a-clock-divider:start [2023/04/18 16:06] (current) – [Prerequisites] Martha
Line 1: Line 1:
 ====== Use Flip-flops to Build a Clock Divider ====== ====== Use Flip-flops to Build a Clock Divider ======
 +A flip-flop is an edge-triggered memory circuit. In this project, we will implement a flip-flop behaviorally using Verilog, and use several flip-flops to create a clock divider that blinks LEDs. 
 +\\
 +\\
 <html> <html>
-<a href="https://reference.digilentinc.com/learn/fundamentals/circuits/memory-circuits/start" class="btn btn-success" role="button" style="position: absolute; right: 0;">Memory Circuits</a>+<a href="/learn/fundamentals/circuits/memory-circuits/start" class="btn btn-success" role="button">Memory Circuits</a>
 </html> </html>
 \\ \\
-A flip-flip is an edge-triggered memory circuit. In this project, we will implement a flip-flop behaviorally using Verilog, and use several flip-flops to create \\  a clock divider that blinks LEDs. +
  
 ===== Prerequisites ==== ===== Prerequisites ====
   * Have the Xilinx ISE WebPACK installed.    * Have the Xilinx ISE WebPACK installed. 
-  * Set up your FPGA board.+  * Set up your [[https://digilent.com/shop/boards-and-components/system-boards/fpga-boards/|FPGA board]].
   * Be able to describe a digital circuit using logic operators.   * Be able to describe a digital circuit using logic operators.
   * Be able to write test bench and simulate circuits using ISim.   * Be able to write test bench and simulate circuits using ISim.
Line 15: Line 18:
 ==== Software ==== ==== Software ====
   * <wrap todo>Xilinx ISE WebPACK</wrap>.   * <wrap todo>Xilinx ISE WebPACK</wrap>.
-  * [[reference/software/adept/start]]+  * [[software:adept:start]]
  
 ==== Hardware ==== ==== Hardware ====
-  * Xilinx ISE compatible board such as [[[[reference/programmable-logic/nexys-4/start]], [[[[reference/programmable-logic/nexys-3/start]], [[reference/programmable-logic/nexys-2/start]], [[reference/programmable-logic/basys-3/start]], or [[reference/programmable-logic/basys-2/start]]+  * Xilinx ISE compatible board such as [[programmable-logic:nexys-4:start]], [[programmable-logic:nexys-3:start]], [[programmable-logic:nexys-2:start]], [[programmable-logic:basys-3:start]], or [[programmable-logic:basys-2:start]]
  
  
Line 24: Line 27:
  
 ===== D Flip-flop (D-FF) ===== ===== D Flip-flop (D-FF) =====
 +A D flip-flop (D-FF) is one of the most fundamental memory devices. A D-FF typically has three inputs: a data input that defines the next state, a timing control \\ input that tells the flip-flop exactly when to "memorize" the data input, and a reset input that can cause the memory to be reset to '0' regardless of the other two inputs (usually referred as asynchronous reset). Figure 1 below displays the block diagram for a D-FF. 
 +\\
 +\\
 <html> <html>
-<a href="https://reference.digilentinc.com/learn/fundamentals/digital-logic/flip-flops/start" class="btn btn-success" role="button" style="position: absolute; right: 0;">D Flip-flop (DFF)</a>+<a href="/learn/fundamentals/digital-logic/flip-flops/start" class="btn btn-success" role="button">D Flip-flop (DFF)</a>
 </html> </html>
 \\ \\
-A D flip-flop (D-FF) is one of the most fundamental memory devices. A D-FF typically has three inputs: a data input that defines the next state, a timing control input that tells the flip-flop exactly when to "memorize" the data input, and a reset input that can cause the memory to be reset to '0' regardless of the other two inputs (usually referred as asynchronous reset). Figure 1 below displays the block diagram for a D-FF.  
  
 {{ :learn:programmable-logic:tutorials:use-flip-flops-to-build-a-clock-divider:dff.png?direct |Figure 1. D-FF block diagram.}} {{ :learn:programmable-logic:tutorials:use-flip-flops-to-build-a-clock-divider:dff.png?direct |Figure 1. D-FF block diagram.}}
Line 267: Line 272:
   - Can you add two switches to control how fast the LED blinks: Say, if switch[1:0] is 0, LED blink frequency is 0.745 Hz; if switch[1:0] is 1, LED blink frequency is 1.49 Hz; if switch[1:0] is 2, LED blink frequency is 2.98 Hz; if switch[1:0] is 3, LED blink frequency is 5.96 Hz.   - Can you add two switches to control how fast the LED blinks: Say, if switch[1:0] is 0, LED blink frequency is 0.745 Hz; if switch[1:0] is 1, LED blink frequency is 1.49 Hz; if switch[1:0] is 2, LED blink frequency is 2.98 Hz; if switch[1:0] is 3, LED blink frequency is 5.96 Hz.
  
-{{tag>learn programmable-logic tutorial nexys-4 nexys-3 nexys-2 basys-3 basys-2 flip-flops clock divider}}+{{tag>learn programmable-logic project nexys-4 nexys-3 nexys-2 basys-2 flip-flops clock divider}}