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learn:programmable-logic:tutorials:use-flip-flops-to-build-a-clock-divider:start [2016/07/22 19:48] – Marthalearn:programmable-logic:tutorials:use-flip-flops-to-build-a-clock-divider:start [2016/07/22 19:49] – Martha
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 ====== Use Flip-flops to Build a Clock Divider ====== ====== Use Flip-flops to Build a Clock Divider ======
 A flip-flip is an edge-triggered memory circuit. In this project, we will implement a flip-flop behaviorally using Verilog, and use several flip-flops to create a clock divider that blinks LEDs.  A flip-flip is an edge-triggered memory circuit. In this project, we will implement a flip-flop behaviorally using Verilog, and use several flip-flops to create a clock divider that blinks LEDs. 
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 ===== D Flip-flop (D-FF) ===== ===== D Flip-flop (D-FF) =====
 A D flip-flop (D-FF) is one of the most fundamental memory devices. A D-FF typically has three inputs: a data input that defines the next state, a timing control \\ input that tells the flip-flop exactly when to "memorize" the data input, and a reset input that can cause the memory to be reset to '0' regardless of the other two inputs (usually referred as asynchronous reset). Figure 1 below displays the block diagram for a D-FF.  A D flip-flop (D-FF) is one of the most fundamental memory devices. A D-FF typically has three inputs: a data input that defines the next state, a timing control \\ input that tells the flip-flop exactly when to "memorize" the data input, and a reset input that can cause the memory to be reset to '0' regardless of the other two inputs (usually referred as asynchronous reset). Figure 1 below displays the block diagram for a D-FF. 
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