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learn:programmable-logic:tutorials:nexys-4-ddr-xadc-demo:start [2017/04/28 20:26] – [1. Generate the Project] Andrew Holzerlearn:programmable-logic:tutorials:nexys-4-ddr-xadc-demo:start [2024/04/16 17:22] (current) – [Overview] James Colvin
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 ===== Overview ===== ===== Overview =====
 +<WRAP center round tip 80%>
 +The Nexys 4 DDR was rebranded as the Nexys A7 starting with Revision D starting in 2018. Updated releases of this particular demo project, usable by all versions of both the Nexys 4 DDR and the Nexys A7 can be found in the [[/programmable-logic/nexys-a7/start#example_projects|Nexys A7 Resource center]].
 +</WRAP>
 +
 +==== Description ====
 +
 +This simple XADC Demo project demonstrates a simple usage of the Nexys-4DDR's 
 +XADC port capability. The behavior is as follows:
 + 
 +  * The 16 User LEDs increment from right to left as the voltage difference on the selected XADC pins gets larger.
 +  * The two seven segment displays show the voltage difference on the AD11, AD10, AD2, AD3 pins in volts.
 +  * sw0 and sw1 select which channel to read from 
 +
 ==== Features Used ==== ==== Features Used ====
  
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 ^ Temperature sensor   |  X  |    | ^ Temperature sensor   |  X  |    |
 ^ 10/100 Ethernet PHY   |  X  |    | ^ 10/100 Ethernet PHY   |  X  |    |
- 
-==== Description ==== 
- 
-This simple XADC Demo project demonstrates a simple usage of the Nexys-4DDR's  
-XADC port capability. The behavior is as follows: 
-  
-  * The 16 User LEDs increment from right to left as the voltage difference on the selected XADC pins gets larger. 
-  * The two seven segment displays show the voltage difference on the AD11, AD10, AD2, AD3 pins in volts. 
-  * sw0 and sw1 select which channel to read from  
  
 === Extra Notes === === Extra Notes ===
  
 A version of the project has been ported to ISE 14.7. The project file can be found {{:nexys4-ddr:isenexys4xadc.zip|here}} A version of the project has been ported to ISE 14.7. The project file can be found {{:nexys4-ddr:isenexys4xadc.zip|here}}
 +
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   * **Nexys 4 DDR Support Files**    * **Nexys 4 DDR Support Files** 
     * These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.      * These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks. 
-    * Follow the Wiki guide: [[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]] on how to install Board Support Files for +    * Follow the Wiki guide: [[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]] on how to install Board Support Files for 
 ----- -----
  
 ===== Downloads ===== ===== Downloads =====
-Nexys 4 DDR Support Repository -- [[https://github.com/Digilent/Nexys-4-DDR-XADC/archive/master.zip|ZIP]] [[https://github.com/Digilent/Nexys-4-DDR-XADC|GIT Repo]]+Nexys 4 DDR Support Repository -- [[https://github.com/Digilent/Nexys-4-DDR-XADC/releases/download/v2016.4-1/Nexys-4-DDR-XADC-2016.4-1.zip|ZIP Archive]] [[https://github.com/Digilent/Nexys-4-DDR-XADC|GIT Repo]]
  
 ------- -------
-===== How to... ===== 
  
 +===== Download and Launch the Nexys 4 DDR XADC Demo =====
  
 +>Follow the [[:learn:programmable-logic:tutorials:github-demos:start|Using Digilent Github Demo Projects]] Tutorial. This is an HDL design project, and as such does not support Vivado SDK, select the tutorial options appropriate for a Vivado-only design. As you will not need to set up your circuit to be measured until after the board is programmed, you do not need to return to this guide when prompted to check for extra hardware requirements and setup.
  
-==== 1. Generate the Project ====+===== Using the Nexys 4 DDR XADC Demo =====
  
->1.1) Download the repository linked in the download section and unzip it in the location of your choosing. +==== 1. Applying a Voltage to the XADC Port ====
  
->1.2) Generate the **XADC** project by following this guide before continuing: [[vivado:github|How to Generate a Project from Digilent's Github]] 
- 
-==== 2. Build the Project ==== 
- 
->2.1) Click **Generate Bitstream** on the left hand menu towards the bottom. Vivado will run through both Run Synthesis and Run Implementation before it generates the bitstream automatically.  
-> 
->Note: If you want, you can click each step by itself in the order of **Run Synthesis**, **Run Implementation** and then **Generate Bitstream**. 
-> 
->{{:basys3:buildflow.png?600|}} 
- 
-==== 3. Program the Board ==== 
- 
->3.1) Once you have generated your bit file, Click on the hardware manager and connect to your board by choosing the local server option. 
-> 
->{{:nexys4-ddr:deviceconnected.jpg?600|}} 
- 
->3.2) Click program to load the project onto your Nexys 4 DDR. 
- 
-==== 4. Run the Project ==== 
- 
-This portion will help you run the demo and observe all its features. 
- 
->4.1) Applying a voltage to the XADC port 
-> 
 >For this demo, the AD11P and AD11N pins are used on the JXADC header. We hooked up a signal generator to our pins. All of the other pins were grounded to avoid coupling. >For this demo, the AD11P and AD11N pins are used on the JXADC header. We hooked up a signal generator to our pins. All of the other pins were grounded to avoid coupling.
 > >
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->4.2) Seven Segment Display and LEDs+==== 2. 7-Segment Display and LEDs ====
 > >
 >The 7-Segment display shows the current voltage across the selected xadc pins. The LEDs turn on from right to left as the input voltage increases. >The 7-Segment display shows the current voltage across the selected xadc pins. The LEDs turn on from right to left as the input voltage increases.
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 >{{:nexys:nexys4:xadc4.jpg?300|}} {{:nexys:nexys4:xadc6.jpg?300|}} >{{:nexys:nexys4:xadc4.jpg?300|}} {{:nexys:nexys4:xadc6.jpg?300|}}
  
->4.3) Selecting a channel +==== 3. Selecting a Channel ==== 
-> + 
->To display a different channel on the display and LEDs, change sw0 and sw1 to the desired channel. +>To view the level of a different XADC channel on the display and LEDs, change sw0 and sw1 to the desired channel number.
->+
  
-{{tag>learn programmable-logic tutorial nexys-4-ddr}}+{{tag>learn programmable-logic project nexys-4-ddr}}