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learn:programmable-logic:tutorials:nexys-4-ddr-sram-to-ddr-component:start [2017/10/24 22:01] – [Usage with Other Boards] Arthur Brownlearn:programmable-logic:tutorials:nexys-4-ddr-sram-to-ddr-component:start [2022/09/12 18:09] (current) – changed forum.digilentinc.com to forum.digilent.com Jeffrey
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 ===== Description ===== ===== Description =====
  
-**Note: There is a problem mapping the MIG in ISE. In short, the tools do not see the MIG generated UCF file. This issue can be solved by following the flow found [[http://www.xilinx.com/support/answers/36427.html|here.]] The digilent support thread associated with this issue is [[https://forum.digilentinc.com/topic/1469-map-problem-on-nexys4ddr/|here.]] **+**Note: There is a problem mapping the MIG in ISE. In short, the tools do not see the MIG generated UCF file. This issue can be solved by following the flow found [[https://support.xilinx.com/s/article/36427|here.]] The digilent support thread associated with this issue is [[https://forum.digilent.com/topic/1469-map-problem-on-nexys4ddr/|here.]] **
  
 This component implements a simple asynchronous SRAM interface to DDR2 converter for the Digilent Nexys4-DDR board. It uses the industry-standard SRAM control bus. Read operations are initiated by bringing CEN, OEN and LB/UB low while keeping WEN high. Valid data will be driven out the Data Output port after the specified access time has elapsed. Write operations occur when CEN, WEN and LB/UB are driven low while keeping OEN high. This component implements a simple asynchronous SRAM interface to DDR2 converter for the Digilent Nexys4-DDR board. It uses the industry-standard SRAM control bus. Read operations are initiated by bringing CEN, OEN and LB/UB low while keeping WEN high. Valid data will be driven out the Data Output port after the specified access time has elapsed. Write operations occur when CEN, WEN and LB/UB are driven low while keeping OEN high.
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 //¹If the XADC is used elsewhere in the design, this should be disabled. It is disabled in the Ram2Ddr version of this core// //¹If the XADC is used elsewhere in the design, this should be disabled. It is disabled in the Ram2Ddr version of this core//
  
-This project contains two different components: Ram2Ddr and Ram2DdrXadx. If your design does not use the XADC core anywhere else, you should use the Ram2DdrXadc component. It automatically instantiates the XADC internally to monitor the chip temperature. If your design does use the XADC core, you should use the Ram2Ddr component. You will then have to connect the device_temp line of the Ram2Ddr component to the XADC component, as described on page 122 in version 1.9 of Xilinx's [[http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v1_9/ug586_7Series_MIS.pdf|7 Series FPGAs Memory Interface Solutions Guide (UG586)]].+This project contains two different components: Ram2Ddr and Ram2DdrXadx. If your design does not use the XADC core anywhere else, you should use the Ram2DdrXadc component. It automatically instantiates the XADC internally to monitor the chip temperature. If your design does use the XADC core, you should use the Ram2Ddr component. You will then have to connect the device_temp line of the Ram2Ddr component to the XADC component, as described on page 122 in version 1.9 of Xilinx's [[https://docs.xilinx.com/v/u/1.9-English/ug586_7Series_MIS|7 Series FPGAs Memory Interface Solutions Guide (UG586)]].
  
 Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project. Both are included with the download. Components can either be inserted into a project as a pre-compiled netlist (.ngc), or as sources by copying the VHDL and MIG project files into your project. Both are included with the download.
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 ^ Parameter         ^ Symbol  ^ Min  ^ Max  ^ Unit  ^ ^ Parameter         ^ Symbol  ^ Min  ^ Max  ^ Unit  ^
 | Read cycle time   | tRC     | 210  | -    | ns    | | Read cycle time   | tRC     | 210  | -    | ns    |
-| Write cycle time  | tWR     | 260  | -    | ns    |+| Write cycle time  | tWC     | 260  | -    | ns    |
  
 ===== Usage with Other Boards ===== ===== Usage with Other Boards =====