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learn:programmable-logic:tutorials:htsspisf:start [2020/06/09 09:05] – [SDK Steps to create a bootloader and program the board] Monica Ignat | learn:programmable-logic:tutorials:htsspisf:start [2022/08/01 22:47] (current) – Made note that this guide is only compatible with 2019.1 and older. Will need a newer guide James Colvin | ||
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This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board. | This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board. | ||
- | You can follow the steps presented in the [[https:// | + | You can follow the steps presented in the [[/ |
Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present. | Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present. | ||
=== Hardware === | === Hardware === | ||
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=== Software === | === Software === | ||
* **Xilinx Vivado 2019.1 with the SDK package.** | * **Xilinx Vivado 2019.1 with the SDK package.** | ||
+ | |||
=== Board Support Files === | === Board Support Files === | ||
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* //These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks// | * //These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks// | ||
* //Follow this Wiki guide ([[vivado: | * //Follow this Wiki guide ([[vivado: | ||
+ | |||
+ | <WRAP center round important 80%> | ||
+ | The xilisf library was officially depreciated by Xilinx starting in 2019.2 with the release of Vitis. This guide is only directly compatible with 2019.1 and older versions of the Xilinx software. | ||
+ | </ | ||
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=== 6. Add AXI Quad SPI IP === | === 6. Add AXI Quad SPI IP === | ||
- | From the Add IP option, select AXI Quad SPI IP with the following customization: | + | From the Add IP option, select AXI Quad SPI IP with the following customization: |
{{: | {{: | ||
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=== 2. Configure Bootloader BSP === | === 2. Configure Bootloader BSP === | ||
* Open the BSP project and open system.mss. Click " | * Open the BSP project and open system.mss. Click " | ||
- | * // | + | * // |
* serial_flash_interface = 1(AXI SPI) | * serial_flash_interface = 1(AXI SPI) | ||
Click " | Click " | ||
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* In your newly created bootloader application, | * In your newly created bootloader application, | ||
It is important to note that this value is the offset that the image will have in Flash. \\ | It is important to note that this value is the offset that the image will have in Flash. \\ | ||
+ | |||
NOTE: If you are using the Cmod-A7 try the offset: 0x00300000. | NOTE: If you are using the Cmod-A7 try the offset: 0x00300000. | ||
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{{: | {{: | ||
- | Make sure to re-build the application after making these changes. | + | NOTE: If you are using a board with Macronix flash follow the additional steps: |
+ | |||
+ | * Open **bootloader.c** from the sources and scroll down until you find the call to **XIsf_Initialize**. Double click the function name to highlight it, right click and select "Open Declaration" | ||
+ | * Add the following line somewhere near the top of **xilisf.c** | ||
+ | < | ||
+ | * In **xilisf.c** find the definition for IntelStmDevices[] and add the following: | ||
+ | < | ||
+ | XISF_BYTES256_PER_PAGE, | ||
+ | XISF_NUM_OF_SECTORS64}</ | ||
+ | * Save **xilisf.c** | ||
+ | <WRAP round important 1000px> | ||
+ | ===Important if you are using a board with Macronix flash.=== | ||
+ | The source files that need editing are part of a library (https:// | ||
+ | |||
+ | A more permanent solution is forking the library repository (https:// | ||
+ | </ | ||
+ | |||
+ | * Make sure to re-build the application after making these changes. | ||
=== 3. Program FPGA with bootloader === | === 3. Program FPGA with bootloader === | ||
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{{tag> | {{tag> | ||
- | {{tag> | + |