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learn:programmable-logic:tutorials:htsspisf:start [2020/06/09 07:45] – [Vivado Steps for creating the block design and generate bitstream] Monica Ignatlearn:programmable-logic:tutorials:htsspisf:start [2022/08/01 22:47] (current) – Made note that this guide is only compatible with 2019.1 and older. Will need a newer guide James Colvin
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 This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board. This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board.
-You can follow the steps presented in the  [[https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start#prerequisites|Microblaze tutorial]], and see below the missing steps for adding QSPI Flash and perform all the connections.+You can follow the steps presented in the  [[/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze/start#prerequisites|Microblaze tutorial]], and see below the missing steps for adding QSPI Flash and perform all the connections.
 Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present. Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present.
 === Hardware === === Hardware ===
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 === Software === === Software ===
   * **Xilinx Vivado 2019.1 with the SDK package.**    * **Xilinx Vivado 2019.1 with the SDK package.** 
 +
  
 === Board Support Files === === Board Support Files ===
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     * //These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks//     * //These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks//
     * //Follow this Wiki guide ([[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]  ) on how to install Board Support Files for Vivado//     * //Follow this Wiki guide ([[vivado:boardfiles|Vivado Board Files for Digilent 7-Series FPGA Boards]]  ) on how to install Board Support Files for Vivado//
 +
 +<WRAP center round important 80%>
 +The xilisf library was officially depreciated by Xilinx starting in 2019.2 with the release of Vitis. This guide is only directly compatible with 2019.1 and older versions of the Xilinx software.
 +</WRAP>
  
  
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 === 5. Adding UART IP Block === === 5. Adding UART IP Block ===
  
-  * Go to {{:genesys2:addip.jpg?nolink|}} **Add IP** and search for "UART".+  * Go to **Add IP** and search for "UART".
  
-{{:vivado:mig_17.jpg?500|}}+{{:learn:programmable-logic:tutorials:htsspisf:addip.png?nolink&500|}}
  
   * Select the **AXI Uartlite** IP block.   * Select the **AXI Uartlite** IP block.
  
-{{:vivado:mig_18.jpg?500|}}+{{:learn:programmable-logic:tutorials:htsspisf:addaxiuart.png?nolink&500|}}
  
   * This will add a UART block to the existing design. We need a UART controller to communicate between the terminal window on the Host-PC and the Nexys 4 DDR hardware.   * This will add a UART block to the existing design. We need a UART controller to communicate between the terminal window on the Host-PC and the Nexys 4 DDR hardware.
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 === 6. Add AXI Quad SPI IP === === 6. Add AXI Quad SPI IP ===
-From the Add IP option, select AXI Quad SPI IP with the following customization: Mode - Quad, slave device - Spansion:+From the Add IP option, select AXI Quad SPI IP with the following customization: Mode - Quad, slave device - Spansion (or Macronix for boards with Macronix flash) 
  
 {{:learn:programmable-logic:tutorials:htsspisf:axiquadipsettings.png?nolink&400|}} {{:learn:programmable-logic:tutorials:htsspisf:axiquadipsettings.png?nolink&400|}}
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 === 7. Running Connection Automation for the First Time === === 7. Running Connection Automation for the First Time ===
  
-  * Select the **Run Connection Automation** from the //Designer Assistance// bar message prompt. This will open up the Run Connection Automation window. Select the **ext_reset_in** as shown. A description of the interface will be shown along with available signal options. Select **reset** as the board part interface. +  * Select the **Run Connection Automation** from the //Designer Assistance// bar message prompt. This will open up the Run Connection Automation window. Select all available connections and click **OK**. Completing this step will connect all the IP blocks that have been added and customized up to this point. In addition to performing auto-connection of available IP blocks, a new IP block called **microblaze_0_axi_periph** will be added to our design. Two signal pins **reset** and **sys_clock** will be added as well. The pin signals point to the right indicating that they are inputs to the clock wizard block ( clk_wiz_1) and reset clock wizard block ( rst_clk_wiz_1_100M).
- +
-{{:vivado:mig_20.jpg?500|}} +
- +
-  * Now select all available connections and click **OK**. Completing this step will connect all the IP blocks that have been added and customized up to this point. In addition to performing auto-connection of available IP blocks, a new IP block called **microblaze_0_axi_periph** will be added to our design. Two signal pins **reset** and **sys_clock** will be added as well. The pin signals point to the right indicating that they are inputs to the clock wizard block ( clk_wiz_1) and reset clock wizard block ( rst_clk_wiz_1_100M).+
  
 The **clk_out2** pin will be manually connected later.  The **clk_out2** pin will be manually connected later. 
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 **Do not select Run Connection Automation at this point**. **Do not select Run Connection Automation at this point**.
  
-{{:nexys4-ddr:nexys4ddr-connectionauto.png?direct&500|}}+{{:learn:programmable-logic:tutorials:htsspisf:runconnauto_1.png?nolink&500|}}
  
 === 8. Perform some manual connections/check the connections === === 8. Perform some manual connections/check the connections ===
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 {{:vivado:mig_30.jpg?500|}} {{:vivado:mig_30.jpg?500|}}
  
------ +  * Select the button circled in blue. This is the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** option that will re-arrange the IP blocks in the design.
-=== 11. Second Manual Connection ===+
  
-  * Manually connect **clk_out2** output port signal on the **clk_wiz_1** to the **sys_clk_i** input port on the **mig_7series_0** block. **clk_out2** signal is the //200 Mhz// clock signal we have added during the Clock Wizard Block Automation step. +{{:nexys4-ddr:nexys4ddr-secmancon2.png?direct&500|}}
  
-{{:vivado:mig_31.jpg?500|}} 
  
-  * Select the button circled in blue. This is the {{:genesys2:regenerate.jpg?nolink|}} **Regenerate Layout** option that will re-arrange the IP blocks in the design.+=== 11. Regenerate layout and validate design ===
  
-{{:nexys4-ddr:nexys4ddr-secmancon2.png?direct&500|}} 
- 
------ 
-=== 12. Regenerate layout and validate design === 
 The result should look like in the below image representing the Block Diagram:{{:learn:programmable-logic:tutorials:htsspisf:bd.png?nolink&800|}} The result should look like in the below image representing the Block Diagram:{{:learn:programmable-logic:tutorials:htsspisf:bd.png?nolink&800|}}
  
-=== 13. Create HDL wrapper ===+=== 12. Create HDL wrapper ===
 Right click on the Block Design, and select the Create HDL Wrapper option. Right click on the Block Design, and select the Create HDL Wrapper option.
  
-=== 14. Synthesize ===+=== 13. Synthesize ===
 Open the synthesized design, and under I/O Ports tab below the page, check the name of the signals to be written in the XDC file. Open the synthesized design, and under I/O Ports tab below the page, check the name of the signals to be written in the XDC file.
  
-=== 15. Create an XDC file and add the constraints in it ===+=== 14. Create an XDC file and add the constraints in it ===
 You can copy paste the syntax from the [[https://github.com/Digilent/digilent-xdc/blob/master/Nexys-4-DDR-Master.xdc|Master XDC file for Nexys4DDR]] You can copy paste the syntax from the [[https://github.com/Digilent/digilent-xdc/blob/master/Nexys-4-DDR-Master.xdc|Master XDC file for Nexys4DDR]]
 --> XDC File signals # --> XDC File signals #
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 </code> </code>
 <-- <--
-=== 16. Compress Bitstream (Optional) ===+=== 15. Compress Bitstream (Optional) ===
 In certain applications (often when using the Cmod A7 with Microblaze) you might find that you do not have the necessary space in flash in order to store both your program and bitstream configuration. If this is the case it would be worth a try to compress your bitstream in order to get it to fit. Note that using a compressed bitstream in flash will not only take up less space but will also improve initial FPGA programming speeds. These steps take place in Vivado before the bitstream gets generated. In certain applications (often when using the Cmod A7 with Microblaze) you might find that you do not have the necessary space in flash in order to store both your program and bitstream configuration. If this is the case it would be worth a try to compress your bitstream in order to get it to fit. Note that using a compressed bitstream in flash will not only take up less space but will also improve initial FPGA programming speeds. These steps take place in Vivado before the bitstream gets generated.
   * With your design ready to be generated into a bitstream select {{:learn:programmable-logic:tutorials:htsspisf:runimplementation.png?nolink&125|}} from the Flow Navigator.   * With your design ready to be generated into a bitstream select {{:learn:programmable-logic:tutorials:htsspisf:runimplementation.png?nolink&125|}} from the Flow Navigator.
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   * Now Vivado has been configured to output a compressed bitstream which will transfer to your SDK project. Select {{:learn:programmable-logic:tutorials:htsspisf:genbit.png?nolink&125|}} and a window might pop up asking you to save your XDC. If so, give the XDC a name and save it. Your bitstream should start generating afterwards.   * Now Vivado has been configured to output a compressed bitstream which will transfer to your SDK project. Select {{:learn:programmable-logic:tutorials:htsspisf:genbit.png?nolink&125|}} and a window might pop up asking you to save your XDC. If so, give the XDC a name and save it. Your bitstream should start generating afterwards.
-===13. Export Hardware Handoff ===+ 
 +===16. Export Hardware Handoff === 
 From File->Export->Export Hardware, make sure to check "Include bitstream" setting:\\ From File->Export->Export Hardware, make sure to check "Include bitstream" setting:\\
  
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 ==== SDK Steps to create a bootloader and program the board ==== ==== SDK Steps to create a bootloader and program the board ====
-===2. Create SPI Bootloader and BSP ===+=== 1. Create SPI Bootloader and BSP ===
   * To create the bootloader, go to //File > New > Application Project//.   * To create the bootloader, go to //File > New > Application Project//.
 Name the bootloader then hit Next.\\ Name the bootloader then hit Next.\\
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 {{:learn:programmable-logic:tutorials:htsspisf:spisrecapp.png?nolink&500|}} {{:learn:programmable-logic:tutorials:htsspisf:spisrecapp.png?nolink&500|}}
  
-===1. Configure Bootloader BSP ===+=== 2. Configure Bootloader BSP ===
  * Open the BSP project and open system.mss. Click "Modify this BSP's Settings". The memory device info needs to be passed to the xilifs library (//Overview > standalone > xilifs//).  * Open the BSP project and open system.mss. Click "Modify this BSP's Settings". The memory device info needs to be passed to the xilifs library (//Overview > standalone > xilifs//).
-  * //serial_flash_family = 5(Spansion/Micron)//+  * //serial_flash_family = 5(Spansion/Micron/Macronix)//
   * serial_flash_interface = 1(AXI SPI)   * serial_flash_interface = 1(AXI SPI)
 Click "Regenerate BSP sources". Click "Regenerate BSP sources".
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 {{:learn:programmable-logic:tutorials:htsspisf:configxilisf.png?nolink&400|}} {{:learn:programmable-logic:tutorials:htsspisf:configxilisf.png?nolink&400|}}
  
-Next we need to update the BSP to use the updated version of **xilisf**. To do this, right click on the BSP and select **Board Support Package settings** and make sure that **xilisf** is checked.+Next we should check that the BSP is updated in order to use the updated version of **xilisf**. To do this, right click on the BSP and select **Board Support Package settings** and make sure that **xilisf** is checked.
  
 {{:learn:programmable-logic:tutorials:htsspisf:xilisf.png?nolink&400|}} {{:learn:programmable-logic:tutorials:htsspisf:xilisf.png?nolink&400|}}
  
-  * In your newly created bootloader application, open **blconfig.h** located in src and change **FLASH_IMAGE_BASEADDR** to suit your needs. +  * In your newly created bootloader application, open **blconfig.h** located in bootloader/src/blconfig.h and change **FLASH_IMAGE_BASEADDR** to suit your needs. Save the file in order to rebuild the bootloader project to contain the latest updates. 
-It is important to note that this value is the offset that the image will have in Flash. +It is important to note that this value is the offset that the image will have in Flash. \\ 
 NOTE: If you are using the Cmod-A7 try the offset: 0x00300000. NOTE: If you are using the Cmod-A7 try the offset: 0x00300000.
  
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 {{:learn:programmable-logic:tutorials:htsspisf:verbose.png?nolink&800|}} {{:learn:programmable-logic:tutorials:htsspisf:verbose.png?nolink&800|}}
  
-Make sure to re-build the application after making these changes.+NOTE: If you are using a board with Macronix flash follow the additional steps:
  
 +  * Open **bootloader.c** from the sources and scroll down until you find the call to **XIsf_Initialize**. Double click the function name to highlight it, right click and select "Open Declaration". This will open **xilisf.c**.
 +  * Add the following line somewhere near the top of **xilisf.c**
 +<code>#define XISF_MACRONIX_DEV_MX25L3233F 0x2016  /**< Device ID for MX25L3233F */ </code>
 +  * In **xilisf.c** find the definition for IntelStmDevices[] and add the following:
 +<code>{XISF_MANUFACTURER_ID_MACRONIX, XISF_MACRONIX_DEV_MX25L3233F,
 +XISF_BYTES256_PER_PAGE, XISF_PAGES256_PER_SECTOR,
 +XISF_NUM_OF_SECTORS64}</code>
 +  * Save **xilisf.c**
 +<WRAP round important 1000px>
 +===Important if you are using a board with Macronix flash.===
 +The source files that need editing are part of a library (https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841939/xilisf) compiled into a bsp/domain. By navigating to the source files in SDK/Vitis, the local copy of the library's source files are opened. Any modification is done on this local copy and build into the static library (and application) upon build. However, when the source files of the bsp/domain are re-generated (context menu, Regenerate BSP sources), the changes made as explained above are overwritten from the originals in the Xilinx install directory. Take care this does not happen.
 +
 +A more permanent solution is forking the library repository (https://github.com/Xilinx/embeddedsw) editing the sources there and including a path to the modified repository in SDK/Vitis Xilinx->Repositories->Global. 
 +</WRAP>
 +
 +  * Make sure to re-build the application after making these changes.
  
 === 3. Program FPGA with bootloader === === 3. Program FPGA with bootloader ===
 +
 The hardware design including bootloader will be programmed into flash such that the FPGA loads it every time it boots. Configure the SPI jumper on the Nexys4 DDR board on the QSPI position. This allows the FPGA to load its bit file from the SPI flash. The FPGA bit file contains the configuration of the FPGA including initial contents of the Microblaze local BRAM. \\ The hardware design including bootloader will be programmed into flash such that the FPGA loads it every time it boots. Configure the SPI jumper on the Nexys4 DDR board on the QSPI position. This allows the FPGA to load its bit file from the SPI flash. The FPGA bit file contains the configuration of the FPGA including initial contents of the Microblaze local BRAM. \\
-Next connect the Nexys4 DDR board via the JTAG usb connector. Start a serial terminal (eg. terraterm) and select the port and set the baud rate to 9600 (as configured in the UARTlite block design).+Next connect the Nexys4 DDR board via the JTAG usb connector. Start a serial terminal (eg. Teraterm) and select the port and set the baud rate to 9600 (as configured in the UARTlite block design).
  
 Select the bootloader.elf file (in the Bootloader/Debug project) instead of "bootloop". Selecting "program" will generate a download.bit file in the "design_wrapper_hw_platform_0" project. Select the bootloader.elf file (in the Bootloader/Debug project) instead of "bootloop". Selecting "program" will generate a download.bit file in the "design_wrapper_hw_platform_0" project.
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 === 4. Flashing FPGA === === 4. Flashing FPGA ===
  
-The **Program Flash Memory** utility will be used again to store the bitstream initialized with the bootloader in BRAM.+The **Program Flash Memory** utility will be used again to store the bitstream initialized with the bootloader in BRAM. Move the jumper on the board in the JTAG position.
 The **Image File** is the **download.bit** that was generated previously, and should be located inside of your hardware platform folder.The **Offset** is 0x0 since the bitstream will be loading our project into memory. Select **Program** to continue. The flash type is "s25fl128sxxxxx0-spi-x1_x2_x4". Check "verify after flash". And finish by clicking "Program". The **Image File** is the **download.bit** that was generated previously, and should be located inside of your hardware platform folder.The **Offset** is 0x0 since the bitstream will be loading our project into memory. Select **Program** to continue. The flash type is "s25fl128sxxxxx0-spi-x1_x2_x4". Check "verify after flash". And finish by clicking "Program".
  
-After flashing you can restart the Nexys4 DDR by pressing the "prog" button. Again the bootloader should start and fail. Note that while the FPGA can load its bit file from flash it can also still be programmed as usual using JTAG.+After flashing you can restart the Nexys4 DDR by pressing the "prog" button. Note that while the FPGA can load its bit file from flash it can also still be programmed as usual using JTAG.
  
 {{:learn:programmable-logic:tutorials:htsspisf:progflash_bit.png?direct&500|}} {{:learn:programmable-logic:tutorials:htsspisf:progflash_bit.png?direct&500|}}
-------+
 === 5. Create a User Application === === 5. Create a User Application ===
 +
 This application will be the one that gets stored into Flash. For this tutorial we will be creating a simple **Hello World** project but the process applies to any project that you would want stored in flash. This application will be the one that gets stored into Flash. For this tutorial we will be creating a simple **Hello World** project but the process applies to any project that you would want stored in flash.
   * Create a **Hello World** application. //File > New > Application Project// and name your app. Then select **Next**.   * Create a **Hello World** application. //File > New > Application Project// and name your app. Then select **Next**.
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 === 6. Configure User App BSP === === 6. Configure User App BSP ===
 +
   * Next we need to make sure to store our program in DDR. In order to do this, right click on the **Hello World** application, and select **Generate Linker Script**.   * Next we need to make sure to store our program in DDR. In order to do this, right click on the **Hello World** application, and select **Generate Linker Script**.
 Place all sections into DDR: Place all sections into DDR:
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 {{:learn:programmable-logic:tutorials:htsspisf:helloconfigxilisf.png?nolink&500|}} {{:learn:programmable-logic:tutorials:htsspisf:helloconfigxilisf.png?nolink&500|}}
------- 
  
 === 7. Program Flash === === 7. Program Flash ===
 +
 In this step we will use the SDK **Program Flash Memory** utility to program our **Hello World** application to Flash. In this step we will use the SDK **Program Flash Memory** utility to program our **Hello World** application to Flash.
  
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 {{tag>learn programmable-logic tutorial nexys-4-ddr nexys-video arty cmod-s6 cmod-a7 microblaze}} {{tag>learn programmable-logic tutorial nexys-4-ddr nexys-video arty cmod-s6 cmod-a7 microblaze}}
-{{tag>learn programmable-logic tutorial genesys-2 microblaze}}+