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learn:programmable-logic:tutorials:htsspisf:start [2020/06/05 09:25] – [Vivado Steps for creating the block design and generate bitstream] Monica Ignat | learn:programmable-logic:tutorials:htsspisf:start [2022/08/01 22:47] (current) – Made note that this guide is only compatible with 2019.1 and older. Will need a newer guide James Colvin | ||
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This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board. | This guide requires the existence of a Vivado project containing a Microblaze system built complete with **Quad SPI**, **External Memory**, and **Uart** cores, and that you have the appropriate QSPI mode jumper setting on the board. | ||
- | You can follow the steps presented in the [[https:// | + | You can follow the steps presented in the [[/ |
Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present. | Since there are slight differences in the Vivado 2019.1 and the version in which the Microblaze tutorial was created, the user needs to check all the connections in the block design to make sure that are correctly made or present. | ||
=== Hardware === | === Hardware === | ||
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=== Software === | === Software === | ||
* **Xilinx Vivado 2019.1 with the SDK package.** | * **Xilinx Vivado 2019.1 with the SDK package.** | ||
+ | |||
=== Board Support Files === | === Board Support Files === | ||
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* //These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks// | * //These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks// | ||
* //Follow this Wiki guide ([[vivado: | * //Follow this Wiki guide ([[vivado: | ||
+ | |||
+ | <WRAP center round important 80%> | ||
+ | The xilisf library was officially depreciated by Xilinx starting in 2019.2 with the release of Vitis. This guide is only directly compatible with 2019.1 and older versions of the Xilinx software. | ||
+ | </ | ||
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* Click on **Create New Project**. Choose the Project Name and Location such that there are **no blank spaces**. This is an important naming convention to follow for project names, file names and location paths. Underscore is a good substitute for empty spaces. It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/ | * Click on **Create New Project**. Choose the Project Name and Location such that there are **no blank spaces**. This is an important naming convention to follow for project names, file names and location paths. Underscore is a good substitute for empty spaces. It is good practice to have a dedicated folder for Vivado Projects, preferably with the smallest possible path length. Example: C:/ | ||
- | {{:vivado:mig_1.jpg?500|}} | + | {{:learn:programmable-logic: |
* Choose Project Type as **RTL Project**. Leave the **Do not specify sources** box unchecked and click **Next**. | * Choose Project Type as **RTL Project**. Leave the **Do not specify sources** box unchecked and click **Next**. | ||
- | {{:vivado:mig_1-1.jpg?500|}} | + | {{:learn:programmable-logic: |
* If you have followed the Board Support File Wiki guide then click next and select **Boards**. From the filter options make required selections for Vendor, Display Name and Board Revision. **Nexys 4 DDR** should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. | * If you have followed the Board Support File Wiki guide then click next and select **Boards**. From the filter options make required selections for Vendor, Display Name and Board Revision. **Nexys 4 DDR** should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors. | ||
- | {{:vivado:mig_2.jpg?500|}} | + | {{:learn:programmable-logic: |
* A summary of the new project design sources and target device is displayed. Click **Finish**. | * A summary of the new project design sources and target device is displayed. Click **Finish**. | ||
- | {{:vivado:mig_3.jpg?500|}} | + | {{:learn:programmable-logic: |
- | ==== 2. Creating New Block Design ==== | + | |
- | >2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. | + | === 2. Creating New Block Design === |
- | > | + | |
- | > | + | |
- | >2.2) On the left you should see the Flow Navigator. Select **Create Block Design** under the IP Integrator. Give a name to your design | + | This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design. |
- | > | + | |
- | > | + | |
- | >2.3) An empty design workspace is created where you can add IP blocks. Add an IP core by clicking on the {{: | + | {{: |
- | > | + | |
- | >{{:vivado:mig_6.jpg?500|}} | + | * On the left you should see the Flow Navigator. Select **Create Block Design** under the IP Integrator. Give a name to your design without any empty spaces. |
+ | |||
+ | {{: | ||
+ | |||
+ | * An empty design workspace is created where you can add IP blocks. Add an IP core by clicking on the {{: | ||
+ | |||
+ | {{:learn:programmable-logic: | ||
----- | ----- | ||
- | === 2. Customize Clock Wizard IP Block === | + | === 3. Adding Microblaze IP and Customization === |
- | Step 4 of the tutorial needs to be modified so it has a new slower | + | |
+ | * This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the **Run Block Automation** message prompt or by double clicking on the block itself. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * Select **Run Block Automation** and a customization assistant window will open with default settings. Change default settings in the block options as shown below and click **OK**. This will customize the block with our new user settings. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * Running the block automation will auto-generate a set of additional IP blocks which will be added to our hardware design automatically based on the options selected in the previous step. **Do not click on Run Connection Automation yet.** | ||
+ | |||
+ | {{: | ||
+ | |||
+ | |||
+ | === 4. Customize Clock Wizard IP Block === | ||
+ | |||
+ | * Double click on the **Clock Wizard** (clk_wiz_1) IP block. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * Choose **sys clock** for CLK_IN1. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * Select the **Output Clocks** tab. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * Select **clk_out2** output frequency as " | ||
+ | |||
+ | {{: | ||
+ | * Select the third clock, having 50MHz frequency: | ||
{{: | {{: | ||
- | === 3. Resume steps at 5 from Microblaze tutorial | + | * The **Port Renaming** tab will give you a summary of the inputs and outputs to the Clock Wizard IP block. Click **OK** to finish block automation of Clock Wizard. **Do not select Run Connection Automation yet**. |
- | Add UARTLite | + | |
- | === 4. Add AXI Quad SPI IP === | + | === 5. Adding UART IP Block === |
- | From the Add IP option, select AXI Quad SPI IP with the following customization: | + | |
- | === 5. Run connection automation and regenerate layout | + | * Go to **Add IP** and search for " |
- | === 6. Perform some manual connections/ | + | |
+ | {{: | ||
+ | |||
+ | * Select the **AXI Uartlite** | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * This will add a UART block to the existing design. We need a UART controller to communicate between the terminal window on the Host-PC and the Nexys 4 DDR hardware. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | === 6. Add AXI Quad SPI IP === | ||
+ | From the Add IP option, select AXI Quad SPI IP with the following customization: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | === 7. Running Connection Automation for the First Time === | ||
+ | |||
+ | * Select the **Run Connection Automation** from the //Designer Assistance// | ||
+ | |||
+ | The **clk_out2** pin will be manually connected later. | ||
+ | |||
+ | **Do not select Run Connection Automation at this point**. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | === 8. Perform some manual connections/ | ||
* Connect the Clocking Wizard " | * Connect the Clocking Wizard " | ||
* Check if the " | * Check if the " | ||
* Check if the Processor System Reset output port " | * Check if the Processor System Reset output port " | ||
- | === 7. Go to step 8 and 9 of the Microblaze Tutorial | + | |
- | The [[https:// | + | === 9. Adding |
+ | |||
+ | * Memory Interface Generator will be the final IP block we will add in our design. | ||
+ | |||
+ | {{:nexys4-ddr:nexys4ddr-addmig.png? | ||
+ | |||
+ | * After adding the MIG IP block, click on **Run Block Automation**. | ||
+ | |||
+ | * Board part interface will be displayed as DDR2_SDRAM. Click **OK** to run the block automation. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for Nexys 4 DDR. Click OK to dismiss this message. You will find the MIG IP block now has additional input and output pins which have to be connected to valid signals. | ||
+ | |||
+ | {{: | ||
Connect the clocking wizard " | Connect the clocking wizard " | ||
- | === 8. Regenerate layout and validate design === | + | === 10. Running Connection Automation for the Second Time === |
+ | |||
+ | * **Now click on Run Connection Automation** message prompt on the //Designer Assistance// | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * **Select only the mig_7series_0 in the connection automation list**. **Do not select Microblaze section in this step**. Click OK. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * New signal connections will be made and displayed. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | * Select the button circled in blue. This is the {{: | ||
+ | |||
+ | {{: | ||
+ | |||
+ | |||
+ | === 11. Regenerate layout and validate design === | ||
The result should look like in the below image representing the Block Diagram: | The result should look like in the below image representing the Block Diagram: | ||
- | === 9. Create HDL wrapper === | + | === 12. Create HDL wrapper === |
Right click on the Block Design, and select the Create HDL Wrapper option. | Right click on the Block Design, and select the Create HDL Wrapper option. | ||
- | === 10. Synthesize === | + | === 13. Synthesize === |
Open the synthesized design, and under I/O Ports tab below the page, check the name of the signals to be written in the XDC file. | Open the synthesized design, and under I/O Ports tab below the page, check the name of the signals to be written in the XDC file. | ||
- | === 11. Create an XDC file and add the constraints in it === | + | === 14. Create an XDC file and add the constraints in it === |
You can copy paste the syntax from the [[https:// | You can copy paste the syntax from the [[https:// | ||
--> XDC File signals # | --> XDC File signals # | ||
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</ | </ | ||
<-- | <-- | ||
- | === 12. Compress Bitstream (Optional) === | + | === 15. Compress Bitstream (Optional) === |
In certain applications (often when using the Cmod A7 with Microblaze) you might find that you do not have the necessary space in flash in order to store both your program and bitstream configuration. If this is the case it would be worth a try to compress your bitstream in order to get it to fit. Note that using a compressed bitstream in flash will not only take up less space but will also improve initial FPGA programming speeds. These steps take place in Vivado before the bitstream gets generated. | In certain applications (often when using the Cmod A7 with Microblaze) you might find that you do not have the necessary space in flash in order to store both your program and bitstream configuration. If this is the case it would be worth a try to compress your bitstream in order to get it to fit. Note that using a compressed bitstream in flash will not only take up less space but will also improve initial FPGA programming speeds. These steps take place in Vivado before the bitstream gets generated. | ||
* With your design ready to be generated into a bitstream select {{: | * With your design ready to be generated into a bitstream select {{: | ||
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* Now Vivado has been configured to output a compressed bitstream which will transfer to your SDK project. Select {{: | * Now Vivado has been configured to output a compressed bitstream which will transfer to your SDK project. Select {{: | ||
- | ===13. Export Hardware Handoff === | + | |
+ | ===16. Export Hardware Handoff === | ||
From File-> | From File-> | ||
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==== SDK Steps to create a bootloader and program the board ==== | ==== SDK Steps to create a bootloader and program the board ==== | ||
- | ===2. Create SPI Bootloader and BSP === | + | === 1. Create SPI Bootloader and BSP === |
* To create the bootloader, go to //File > New > Application Project//. | * To create the bootloader, go to //File > New > Application Project//. | ||
Name the bootloader then hit Next.\\ | Name the bootloader then hit Next.\\ | ||
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{{: | {{: | ||
- | ===1. Configure Bootloader BSP === | + | === 2. Configure Bootloader BSP === |
* Open the BSP project and open system.mss. Click " | * Open the BSP project and open system.mss. Click " | ||
- | * // | + | * // |
* serial_flash_interface = 1(AXI SPI) | * serial_flash_interface = 1(AXI SPI) | ||
Click " | Click " | ||
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{{: | {{: | ||
- | Next we need to update | + | Next we should check that the BSP is updated in order to use the updated version of **xilisf**. To do this, right click on the BSP and select **Board Support Package settings** and make sure that **xilisf** is checked. |
{{: | {{: | ||
- | * In your newly created bootloader application, | + | * In your newly created bootloader application, |
- | It is important to note that this value is the offset that the image will have in Flash. | + | It is important to note that this value is the offset that the image will have in Flash. |
NOTE: If you are using the Cmod-A7 try the offset: 0x00300000. | NOTE: If you are using the Cmod-A7 try the offset: 0x00300000. | ||
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{{: | {{: | ||
- | Make sure to re-build | + | NOTE: If you are using a board with Macronix flash follow |
+ | * Open **bootloader.c** from the sources and scroll down until you find the call to **XIsf_Initialize**. Double click the function name to highlight it, right click and select "Open Declaration" | ||
+ | * Add the following line somewhere near the top of **xilisf.c** | ||
+ | < | ||
+ | * In **xilisf.c** find the definition for IntelStmDevices[] and add the following: | ||
+ | < | ||
+ | XISF_BYTES256_PER_PAGE, | ||
+ | XISF_NUM_OF_SECTORS64}</ | ||
+ | * Save **xilisf.c** | ||
+ | <WRAP round important 1000px> | ||
+ | ===Important if you are using a board with Macronix flash.=== | ||
+ | The source files that need editing are part of a library (https:// | ||
+ | |||
+ | A more permanent solution is forking the library repository (https:// | ||
+ | </ | ||
+ | |||
+ | * Make sure to re-build the application after making these changes. | ||
=== 3. Program FPGA with bootloader === | === 3. Program FPGA with bootloader === | ||
+ | |||
The hardware design including bootloader will be programmed into flash such that the FPGA loads it every time it boots. Configure the SPI jumper on the Nexys4 DDR board on the QSPI position. This allows the FPGA to load its bit file from the SPI flash. The FPGA bit file contains the configuration of the FPGA including initial contents of the Microblaze local BRAM. \\ | The hardware design including bootloader will be programmed into flash such that the FPGA loads it every time it boots. Configure the SPI jumper on the Nexys4 DDR board on the QSPI position. This allows the FPGA to load its bit file from the SPI flash. The FPGA bit file contains the configuration of the FPGA including initial contents of the Microblaze local BRAM. \\ | ||
- | Next connect the Nexys4 DDR board via the JTAG usb connector. Start a serial terminal (eg. terraterm) and select the port and set the baud rate to 9600 (as configured in the UARTlite block design). | + | Next connect the Nexys4 DDR board via the JTAG usb connector. Start a serial terminal (eg. Teraterm) and select the port and set the baud rate to 9600 (as configured in the UARTlite block design). |
Select the bootloader.elf file (in the Bootloader/ | Select the bootloader.elf file (in the Bootloader/ | ||
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=== 4. Flashing FPGA === | === 4. Flashing FPGA === | ||
- | The **Program Flash Memory** utility will be used again to store the bitstream initialized with the bootloader in BRAM. | + | The **Program Flash Memory** utility will be used again to store the bitstream initialized with the bootloader in BRAM. Move the jumper on the board in the JTAG position. |
The **Image File** is the **download.bit** that was generated previously, and should be located inside of your hardware platform folder.The **Offset** is 0x0 since the bitstream will be loading our project into memory. Select **Program** to continue. The flash type is " | The **Image File** is the **download.bit** that was generated previously, and should be located inside of your hardware platform folder.The **Offset** is 0x0 since the bitstream will be loading our project into memory. Select **Program** to continue. The flash type is " | ||
- | After flashing you can restart the Nexys4 DDR by pressing the " | + | After flashing you can restart the Nexys4 DDR by pressing the " |
{{: | {{: | ||
- | ------ | + | |
=== 5. Create a User Application === | === 5. Create a User Application === | ||
+ | |||
This application will be the one that gets stored into Flash. For this tutorial we will be creating a simple **Hello World** project but the process applies to any project that you would want stored in flash. | This application will be the one that gets stored into Flash. For this tutorial we will be creating a simple **Hello World** project but the process applies to any project that you would want stored in flash. | ||
* Create a **Hello World** application. //File > New > Application Project// and name your app. Then select **Next**. | * Create a **Hello World** application. //File > New > Application Project// and name your app. Then select **Next**. | ||
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=== 6. Configure User App BSP === | === 6. Configure User App BSP === | ||
+ | |||
* Next we need to make sure to store our program in DDR. In order to do this, right click on the **Hello World** application, | * Next we need to make sure to store our program in DDR. In order to do this, right click on the **Hello World** application, | ||
Place all sections into DDR: | Place all sections into DDR: | ||
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{{: | {{: | ||
- | ------ | ||
=== 7. Program Flash === | === 7. Program Flash === | ||
+ | |||
In this step we will use the SDK **Program Flash Memory** utility to program our **Hello World** application to Flash. | In this step we will use the SDK **Program Flash Memory** utility to program our **Hello World** application to Flash. | ||
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{{tag> | {{tag> | ||
- | {{tag> | + |