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learn:programmable-logic:tutorials:arty-getting-started-with-microblaze:start [2016/05/10 16:19] – created Sam K | learn:programmable-logic:tutorials:arty-getting-started-with-microblaze:start [2017/10/20 20:26] (current) – Arthur Brown | ||
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- | ====== Getting Started with Microblaze ====== | + | ====== |
+ | |||
+ | <WRAP round important 660px> | ||
+ | === Important! === | ||
+ | This guide is obsolete, the updated guide can be found [[: | ||
+ | </ | ||
{{ : | {{ : | ||
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* Displayed the final output on both the SDK console and Tera Term | * Displayed the final output on both the SDK console and Tera Term | ||
- | ----- | ||
- | ===== Prerequisites ===== | + | ==== Introduction |
- | + | ||
- | === Skills === | + | |
- | * **Familiarity with Vivado** | + | |
- | * **Block Design Experience** | + | |
- | + | ||
- | === Hardware === | + | |
- | * **Digilent Arty FPGA Board** | + | |
- | * **Micro USB Cable** | + | |
- | * //Used for UART communication and JTAG programming// | + | |
- | + | ||
- | === Software === | + | |
- | * **Xilinx Vivado 2015.X with the SDK package.** | + | |
- | + | ||
- | === Board Support Files === | + | |
- | * **Arty Support Files** | + | |
- | * //These files will describe GPIO interfaces on your board and make it easier | + | |
- | * //Follow this Wiki guide **[[vivado: | + | |
- | + | ||
- | ----- | + | |
- | + | ||
- | + | ||
- | ===== Introduction ===== | + | |
Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool. | Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add a Microblaze IP block using the Vivado IP Integrator tool. | ||
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Finally, a UART ( universal asynchronous receiver/ | Finally, a UART ( universal asynchronous receiver/ | ||
- | ----- | + | ==== General |
- | + | ||
- | ===== General Design Flow ===== | + | |
- | I. Vivado | + | **I. Vivado** |
* Open Vivado and select Arty board | * Open Vivado and select Arty board | ||
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We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado. | We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado. | ||
- | II. SDK | + | **II. SDK** |
* Create new application project and select default Hello World template | * Create new application project and select default Hello World template | ||
* Program FPGA | * Program FPGA | ||
* Run configuration by selecting the correct UART COM Port and Baud Rate | * Run configuration by selecting the correct UART COM Port and Baud Rate | ||
+ | |||
+ | ----- | ||
+ | |||
+ | ===== Prerequisites ===== | ||
+ | |||
+ | === Skills === | ||
+ | * **Familiarity with Vivado** | ||
+ | * **Block Design Experience** | ||
+ | |||
+ | === Hardware === | ||
+ | * **Digilent Arty FPGA Board** | ||
+ | * **Micro USB Cable** | ||
+ | * //Used for UART communication, | ||
+ | |||
+ | === Software === | ||
+ | * **Xilinx Vivado 2015.4 with the SDK package.** | ||
+ | * //Newer versions of Vivado may also work// | ||
+ | * **Digilent Board Support Files** | ||
+ | * //Follow the **[[vivado: | ||
----- | ----- | ||
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> | > | ||
> | > | ||
+ | |||
+ | / |