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| learn:courses:unit-2:start [2017/04/13 19:55] – [7.6. Finite State Machines] Martha | learn:courses:unit-2:start [2021/10/13 22:21] (current) – Arthur Brown | ||
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| ====== Unit 2: Elements of Real-time Systems ====== | ====== Unit 2: Elements of Real-time Systems ====== | ||
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| ==Unit 2 Labs== | ==Unit 2 Labs== | ||
| - | * [[https:// | + | * [[/ |
| - | * [[https:// | + | * [[/ |
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| ===== 2. Objectives: ===== | ===== 2. Objectives: ===== | ||
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| ===== 3. Basic Knowledge: ===== | ===== 3. Basic Knowledge: ===== | ||
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| ===== 4. Unit Equipment List ===== | ===== 4. Unit Equipment List ===== | ||
| ==== 4.1. Hardware ==== | ==== 4.1. Hardware ==== | ||
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| ==== 4.2. Software ==== | ==== 4.2. Software ==== | ||
| The following programs must be installed on your development workstation: | The following programs must be installed on your development workstation: | ||
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| ===== 5. Project Takeaways ===== | ===== 5. Project Takeaways ===== | ||
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| The correct operation of a dynamic real-time scheduling scheme is predicated on two requirements. The first is that the worst case (longest) execution time of the timer interrupt service routine (ISR) must be less than the interrupt interval. The second is that the time remaining in the interrupt period after execution of the ISR must be sufficient so that it appears to the user that the processor is acknowledging his or her inputs in a timely manner. | The correct operation of a dynamic real-time scheduling scheme is predicated on two requirements. The first is that the worst case (longest) execution time of the timer interrupt service routine (ISR) must be less than the interrupt interval. The second is that the time remaining in the interrupt period after execution of the ISR must be sufficient so that it appears to the user that the processor is acknowledging his or her inputs in a timely manner. | ||
| - | Real-time operation has two basic requirements: | + | Real-time operation has two basic requirements: |
| The time required to service the ISR includes the execution time of the user ISR code in addition to the time required to save and restore the system context. Using the MPLAB X Stopwatch debugging feature, we find that it requires 33 machine cycles to save and restore the system context. Using a core frequency of 80 MHz, the context saving and restoring time is 1.03 μs. The time to execute the user written code varies. In the case of Labs 2a and 2b, execution of the ISR code will vary based upon the conditional execution of the LED and stepper motor functions. | The time required to service the ISR includes the execution time of the user ISR code in addition to the time required to save and restore the system context. Using the MPLAB X Stopwatch debugging feature, we find that it requires 33 machine cycles to save and restore the system context. Using a core frequency of 80 MHz, the context saving and restoring time is 1.03 μs. The time to execute the user written code varies. In the case of Labs 2a and 2b, execution of the ISR code will vary based upon the conditional execution of the LED and stepper motor functions. | ||
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| ==== Listing 7.6. Timer 1 ISR at Interrupt Level 2 ==== | ==== Listing 7.6. Timer 1 ISR at Interrupt Level 2 ==== | ||
| < | < | ||
| - | void __ISR(_TIMER_1_VECTOR, | + | void __ISR(_TIMER_1_VECTOR, |
| { | { | ||
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| Transitions describe both events (triggers) with guards and actions associated with the transaction. Guards represent conditions that inhibit the transaction. There may be multiple transitions between the same two states. Each path represents differing guard conditions and differing transaction actions. | Transitions describe both events (triggers) with guards and actions associated with the transaction. Guards represent conditions that inhibit the transaction. There may be multiple transitions between the same two states. Each path represents differing guard conditions and differing transaction actions. | ||
| - | {{ : | + | {{ : |
| //Figure 7.2. State diagram for a push-on / push-off button operation.// | //Figure 7.2. State diagram for a push-on / push-off button operation.// | ||
| - | are needed for a button press and release when the switch is on, as well as when the switch is off. There is only one possible event that initiates a transition: the clock event, which for this example is a millisecond timer. The number of clock pulses is counted to hold the system in a fixed state until the predefined delay period has expired. This is used to eliminate multiple transitions due to [[http:// | + | The button action described by Fig. 7.2 shows that four states are required to represent its operation: two states |
| The guard condition on the clock event inhibits the transition between states unless the button is in the proper pressed or released condition. The action associated with the transaction controls an LED to indicate the condition of the push-on/ | The guard condition on the clock event inhibits the transition between states unless the button is in the proper pressed or released condition. The action associated with the transaction controls an LED to indicate the condition of the push-on/ | ||
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| { | { | ||
| case 0: | case 0: | ||
| - | if(button) / | + | if(button) / |
| { | { | ||
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| ==== Listing A.1. Millisecond Delay Based on Polling the Core Timer ==== | ==== Listing A.1. Millisecond Delay Based on Polling the Core Timer ==== | ||
| < | < | ||
| - | #define CORE_MS_TICK_RATE CORE_OSCILLATOR_FREQUERNCY/2/1000 | + | #define CORE_MS_TICK_RATE CORE_OSCILLATOR_FREQUENCY/2/1000 |
| void msDelay(unsigned int mS) | void msDelay(unsigned int mS) | ||
| { | { | ||
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| Refer to Section 2.12 of the [[http:// | Refer to Section 2.12 of the [[http:// | ||
| - | {{ : | + | {{ : |
| //Figure A.1. Core timer block diagram.// | //Figure A.1. Core timer block diagram.// | ||
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| ==== A.3. Types of Timers ==== | ==== A.3. Types of Timers ==== | ||
| [[http:// | [[http:// | ||
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| Timers 1 through 5 are 16-bit timers which support both synchronous external timer modes of operation. Timer 1 also allows asynchronous external mode which enables operations during sleep mode when the master oscillator is turned off and controller operation is done using a secondary oscillator. | Timers 1 through 5 are 16-bit timers which support both synchronous external timer modes of operation. Timer 1 also allows asynchronous external mode which enables operations during sleep mode when the master oscillator is turned off and controller operation is done using a secondary oscillator. | ||
| - | + | {{ : | |
| - | {{ : | + | |
| //Figure A.2. Simplified PIC32 timer block diagram.// | //Figure A.2. Simplified PIC32 timer block diagram.// | ||
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| The maximum counter value is determined by the size of the register that holds the counts. Common sizes for microprocessors are 8-, 16-, and 32-bit. Including the core timer, the PIC32 processor has six timers that can be used for delay timing. The core timer is 32 bits wide. Timers 2 and 3 along with Timers 4 and 5 can be used together as 32-bit counters, respectively, | The maximum counter value is determined by the size of the register that holds the counts. Common sizes for microprocessors are 8-, 16-, and 32-bit. Including the core timer, the PIC32 processor has six timers that can be used for delay timing. The core timer is 32 bits wide. Timers 2 and 3 along with Timers 4 and 5 can be used together as 32-bit counters, respectively, | ||
| - | The period register is used to set the timer’s maximum count. If a period equal to a value of N is set, then N-1 is written to the PR register. The period registers are declared as PR1 for Timer 1, PR2 for Timer 2, and so on. Each Timer 1 count is compared to the value of the PR1 register. When the PR1 register equals the Timer 1 register, the timer has reached its terminal count and initiates two actions: first, the Timer 1 register is reset to zero, and second, the Timer 1 Interrupt Flag (T1IF) bit is set in the Interrupt Flag Status register (IFS0). (See the [[http:// | + | The period register is used to set the timer’s maximum count. If a period equal to a value of N is set, then N-1 is written to the PR register. The period registers are declared as PR1 for Timer 1, PR2 for Timer 2, and so on. Each Timer 1 count is compared to the value of the PR1 register. When the PR1 register equals the Timer 1 register, the timer has reached its terminal count and initiates two actions: first, the Timer 1 register is reset to zero, and second, the Timer 1 Interrupt Flag (T1IF) bit is set in the Interrupt Flag Status register (IFS0). (See the [[http:// |
| As Fig. A.3 illustrates, | As Fig. A.3 illustrates, | ||
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| $$T1CLK = (XTAL * FPLLMUL / ( FPLLIDIV * FPLLODIV * FPBDIV )) / TCKPS) | $$T1CLK = (XTAL * FPLLMUL / ( FPLLIDIV * FPLLODIV * FPBDIV )) / TCKPS) | ||
| - | {{ : | + | {{ : |
| //Figure A.3. Divider chain from the CPU crystal (oscillator) to the Timer 1 Interrupt flag.// | //Figure A.3. Divider chain from the CPU crystal (oscillator) to the Timer 1 Interrupt flag.// | ||
| - | Since the Timer 1 register is reset to zero, the value set into the PR register is one less than the desired number of Timer 1 clock counts. Hence, the rate that the timer interrupt flag is set equals the timer clock frequency divided by the value written to the PR register, as expressed by Eq. 2. For example, using the values shown in Fig. A.4, the T1PS is set for 8 and the PR1 register is set to 24999. The result of these settings is that the T1 interrupt flag is set at the rate of 50 Hz, provided that the subsequent interrupt flag is cleared in software. The T1IF can be polled or used to generate interrupts. Timers 2 through 5 are similar to Timer 1, with the differences being the timer pre-scale options and the period register. | + | Since the Timer 1 register is reset to zero, the value set into the PR register is one less than the desired number of Timer 1 clock counts. Hence, the rate that the timer interrupt flag is set equals the timer clock frequency divided by the value written to the PR register, as expressed by Eq. 2. For example, using the values shown in Fig. A.3, the T1PS is set for 8 and the PR1 register is set to 24999. The result of these settings is that the T1 interrupt flag is set at the rate of 50 Hz, provided that the subsequent interrupt flag is cleared in software. The T1IF can be polled or used to generate interrupts. Timers 2 through 5 are similar to Timer 1, with the differences being the timer pre-scale options and the period register. |
| ==== A.5. Timer Interrupts ==== | ==== A.5. Timer Interrupts ==== | ||
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| * | * | ||
| * Oscillator Configuration Bit Settings: config_bits.h | * Oscillator Configuration Bit Settings: config_bits.h | ||
| - | * Basys MX3 hardware initialization is provided by Hardware_Setup.c | + | * Basys MX3 hardware initialization is provided by hardware.c and should be included as a project source file. |
| * Notes: | * Notes: | ||
| * - Peripheral clock: BPCLK = FOSC/PB_DIV = 80E6/8 = 10MHz | * - Peripheral clock: BPCLK = FOSC/PB_DIV = 80E6/8 = 10MHz | ||
| * - Timer 1 clock = T1_CLK = PBCLK / T1PS = 10E6 / 8 = 1.25E5 | * - Timer 1 clock = T1_CLK = PBCLK / T1PS = 10E6 / 8 = 1.25E5 | ||
| - | * - To generate a 1 ms delay, PR1 is loaded with T1_TICK = (10000-1) = 9999 | + | * - To generate a 1 ms delay, PR1 is loaded with T1_TICK |
| * | * | ||
| ********************************************************************/ | ********************************************************************/ | ||
| - | #include " | ||
| #include < | #include < | ||
| + | #include " | ||
| + | #include " | ||
| /* Application constant */ | /* Application constant */ | ||
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| /* Configure Timer1 to roll over once each second */ | /* Configure Timer1 to roll over once each second */ | ||
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| while (1) | while (1) | ||
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| } /* End of File main.c */ | } /* End of File main.c */ | ||
| </ | </ | ||
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| / | / | ||
| * The purpose of this example code is to demonstrate the use of the Type A | * The purpose of this example code is to demonstrate the use of the Type A | ||
| - | * Timer 1 interrupts to generate a 1 ms delay. | + | * Timer 1 interrupts to generate a 1 second |
| * | * | ||
| * Platform: | * Platform: | ||
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| * | * | ||
| * Oscillator Configuration Bit Settings: config_bits.h | * Oscillator Configuration Bit Settings: config_bits.h | ||
| - | * Basys MX3 hardware initialization is provided by Hardware_Setup.c | + | * Basys MX3 hardware initialization is provided by hardware.c |
| * Notes: | * Notes: | ||
| * - Peripheral Clock: PBCLK = 80E6 / 8 = 10E6 | * - Peripheral Clock: PBCLK = 80E6 / 8 = 10E6 | ||
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| * | * | ||
| ********************************************************************/ | ********************************************************************/ | ||
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| + | #include < | ||
| #include " | #include " | ||
| - | # | + | # |
| /* Application constant */ | /* Application constant */ | ||
| - | #define T1_PRESCALE | + | #define T1_PRESCALE |
| - | #define TOGGLES_PER_SEC | + | #define TOGGLES_PER_SEC |
| #define T1_TICK | #define T1_TICK | ||
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| /* Code background tasks */ | /* Code background tasks */ | ||
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| } /* End of main */ | } /* End of main */ | ||
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| * SYNTAX: | * SYNTAX: | ||
| * KEYWORDS: | * KEYWORDS: | ||
| - | * DESCRIPTION: | + | * DESCRIPTION: |
| * Parameters: | * Parameters: | ||
| * RETURN: | * RETURN: | ||
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| /* End of File main.c | /* End of File main.c | ||
| </ | </ | ||
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| + | ---- | ||
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| + | [[{}learn/ | ||
| + | [[{}/ | ||
| + | [[{}/ | ||
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| ---- | ---- | ||
| {{tag> | {{tag> | ||