Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revision | ||
learn:courses:microprocessor-io-unit-1:start [2017/04/24 13:16] – [5. Project Takeaways] Talesa Bleything | learn:courses:microprocessor-io-unit-1:start [2021/10/13 15:24] (current) – Arthur Brown | ||
---|---|---|---|
Line 2: | Line 2: | ||
[[{}/ | [[{}/ | ||
==Unit 1 Labs== | ==Unit 1 Labs== | ||
- | * [[https:// | + | * [[/ |
- | * [[https:// | + | * [[/ |
== Download This Document == | == Download This Document == | ||
- | * {{ : | + | {{ : |
Line 16: | Line 16: | ||
===== 2. Objectives ===== | ===== 2. Objectives ===== | ||
- | | + | |
- | | + | |
- | | + | |
- | | + | |
Line 25: | Line 25: | ||
===== 3. Basic Knowledge ===== | ===== 3. Basic Knowledge ===== | ||
- | | + | |
- | | + | |
- | | + | |
- | | + | |
Line 35: | Line 35: | ||
===== 4. Equipment List ===== | ===== 4. Equipment List ===== | ||
==== 4.1. Hardware ==== | ==== 4.1. Hardware ==== | ||
- | | + | |
- | | + | |
- | | + | |
In addition, we suggest the following instruments: | In addition, we suggest the following instruments: | ||
- | | + | |
==== 4.2. Software ==== | ==== 4.2. Software ==== | ||
The following programs must be installed on your development workstation: | The following programs must be installed on your development workstation: | ||
- | | + | |
* [[http:// | * [[http:// | ||
* [[http:// | * [[http:// | ||
- | | + | |
- | | + | |
Line 55: | Line 55: | ||
===== 5. Project Takeaways ===== | ===== 5. Project Takeaways ===== | ||
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
- | | + | |
Line 126: | Line 126: | ||
//Figure 8.1. Integrated Development Hardware Diagram.// | //Figure 8.1. Integrated Development Hardware Diagram.// | ||
- | The diagram in Fig. 8.1 shows the Basys MX3 unit. The Basys MX3 has a built-in programmer/ | + | The diagram in Fig. 8.1 shows the Basys MX3 unit. The Basys MX3 has a built-in programmer/ |
==== 8.2. General Notes of Interest ==== | ==== 8.2. General Notes of Interest ==== | ||
Line 138: | Line 138: | ||
#define _SUPPRESS_PLIB_WARNING | #define _SUPPRESS_PLIB_WARNING | ||
#endif | #endif | ||
- | | + | |
- | # | + | #ifndef _DISABLE_OPENADC10_CONFIGPORT_WARNING |
- | #endif | + | # |
+ | #endif | ||
</ | </ | ||
< | < | ||
<ol start=" | <ol start=" | ||
- | < | + | < |
**Table 8.1. XC32 (Global Options) all Options Category.** | **Table 8.1. XC32 (Global Options) all Options Category.** | ||
Line 156: | Line 157: | ||
< | < | ||
<ol start=" | <ol start=" | ||
- | < | + | < |
==== 8.3. Microcontroller Resources ==== | ==== 8.3. Microcontroller Resources ==== | ||
Line 190: | Line 191: | ||
- Right-click on the Header Files and select “New” -> “XC32 Header.h”. Name this file “config_bits.h”. | - Right-click on the Header Files and select “New” -> “XC32 Header.h”. Name this file “config_bits.h”. | ||
- Click on “Windows” -> “PIC Memory Views” -> “Configuration Bits”. | - Click on “Windows” -> “PIC Memory Views” -> “Configuration Bits”. | ||
- | - Set the options as shown in Listing | + | - Set the options as shown in Listing |
- Click on “Generate Source Code to Output”. | - Click on “Generate Source Code to Output”. | ||
- Enter “CTRL A” to highlight the text in the output window and “CTRL C” to copy the text. | - Enter “CTRL A” to highlight the text in the output window and “CTRL C” to copy the text. | ||
Line 210: | Line 211: | ||
==== Listing A.1. Format of a Typical Main Function ==== | ==== Listing A.1. Format of a Typical Main Function ==== | ||
< | < | ||
- | int main(int argc, char** argv) | + | int main(int argc, char** argv) |
{ | { | ||
// Initialization code goes here | // Initialization code goes here | ||
Line 529: | Line 530: | ||
@File Name | @File Name | ||
- | PICmx370.c | + | hardware.c |
| | ||
Line 548: | Line 549: | ||
#include " | #include " | ||
- | #include " | ||
#include < | #include < | ||
Line 595: | Line 595: | ||
| | ||
- | | + | |
| | ||
- | | + | |
} /* End of hardware_setup */ | } /* End of hardware_setup */ | ||
Line 643: | Line 643: | ||
If the bit in the TRIS register is set low to make the I/O pin to function as an output, the voltage pin can be set high by writing a 1 to the appropriate bit in the LAT register. Setting the LAT register bit to a zero sets the output pin low (0V). The actual voltage at the output pin depends on the setting in the ODC register. The default configuration has all bits in the ODC register set to zero, which means the output can both source (supply output current) and sink (pull outputs low) current. If the bit in the ODC register is set high, then the output pin functions as open drain, which can sink current but not source current. | If the bit in the TRIS register is set low to make the I/O pin to function as an output, the voltage pin can be set high by writing a 1 to the appropriate bit in the LAT register. Setting the LAT register bit to a zero sets the output pin low (0V). The actual voltage at the output pin depends on the setting in the ODC register. The default configuration has all bits in the ODC register set to zero, which means the output can both source (supply output current) and sink (pull outputs low) current. If the bit in the ODC register is set high, then the output pin functions as open drain, which can sink current but not source current. | ||
- | The maximum current capability of each conventional I/O pin is 15mA (sink or source), while the combined current of all I/O pins is 200mA subject to total power constraints. I/O pins have both open drain and active source output capability. The open drain capability provided by the ODC register is useful when interfacing with switch array keypads (see [[http://store.digilentinc.com/pmodkypd-16-button-keypad/ | + | The maximum current capability of each conventional I/O pin is 15mA (sink or source), while the combined current of all I/O pins is 200mA subject to total power constraints. I/O pins have both open drain and active source output capability. The open drain capability provided by the ODC register is useful when interfacing with switch array keypads (see [[https://digilent.com/shop/ |
The PORT register allows the state of pin to be read regardless if the pin is configured in the TRIS register to be an input or an output. If the voltage on the pin is above the high input threshold, the PORT bit is read as a logic one. Various processor pins have different thresholds. | The PORT register allows the state of pin to be read regardless if the pin is configured in the TRIS register to be an input or an output. If the voltage on the pin is above the high input threshold, the PORT bit is read as a logic one. Various processor pins have different thresholds. | ||
Line 657: | Line 657: | ||
{ | { | ||
// Initialization | // Initialization | ||
- | ANSELDbits.ANSD1 = 0; // RD1 set to digital I/O | + | ANSELDbits.ANSD1 = 0; |
- | TRISDbits.TRISD1 = 0; // RD1 set to output | + | TRISDbits.TRISD1 = 0; |
- | TRISDbits.TRISD0 = 1; // RD2 set to input | + | TRISDbits.TRISD0 = 1; |
// loop | // loop | ||
Line 665: | Line 665: | ||
{ | { | ||
LATDbits.LATD1 = PORTDbits.RD0; | LATDbits.LATD1 = PORTDbits.RD0; | ||
- | | + | |
} | } | ||
</ | </ | ||
Line 676: | Line 676: | ||
// Initialization | // Initialization | ||
ANSELDCLR = 0x02; // RD1 set to digital I/O | ANSELDCLR = 0x02; // RD1 set to digital I/O | ||
- | TRISDCLR = 0x02; // RD1 set to output | + | TRISDCLR = 0x02; |
TRISDSET = 0x01; // RD0 set to input | TRISDSET = 0x01; // RD0 set to input | ||
Line 683: | Line 683: | ||
{ | { | ||
if(PORTD & 0x01) // Read RD0 pin | if(PORTD & 0x01) // Read RD0 pin | ||
- | | + | |
else | else | ||
- | | + | |
- | | + | |
} | } | ||
</ | </ | ||
Line 718: | Line 718: | ||
| 84 | RD7 | RPD7/ | | 84 | RD7 | RPD7/ | ||
| 80 | RD13 | RPD13/ | | 80 | RD13 | RPD13/ | ||
- | | 95 | + | | 95 |
| 93 | RE0 | PMD0/ | | 93 | RE0 | PMD0/ | ||
| 94 | RE1 | PMD1/ | | 94 | RE1 | PMD1/ | ||
Line 761: | Line 761: | ||
| 77 | RD2 | AN25/ | | 77 | RD2 | AN25/ | ||
| 88 | RF1 | RPF1/ | | 88 | RF1 | RPF1/ | ||
- | | 25 | RB0 | PGED1/ | + | | 25 | RB0 | PGED1/ |
- | | 24 | RB1 | PGC1/ | + | | 24 | RB1 | PGC1/ |
| 57 | RG2 | SCL1/ | | 57 | RG2 | SCL1/ | ||
| 56 | RG3 | SDA1/ | | 56 | RG3 | SDA1/ |