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learn:courses:microprocessor-io-unit-1:start [2017/03/21 16:59] – [Appendix E: PIC32MX370F512L Processor Pin Assignments for Basys MX3A] Martha | learn:courses:microprocessor-io-unit-1:start [2021/10/13 22:24] (current) – Arthur Brown | ||
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- | ====== Unit 1: Microprocessor | + | ====== Unit 1: Microprocessor |
+ | [[{}/ | ||
==Unit 1 Labs== | ==Unit 1 Labs== | ||
- | * [[https:// | + | * [[/ |
- | * [[https:// | + | * [[/ |
== Download This Document == | == Download This Document == | ||
- | * {{ : | + | {{ : |
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===== 2. Objectives ===== | ===== 2. Objectives ===== | ||
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===== 3. Basic Knowledge ===== | ===== 3. Basic Knowledge ===== | ||
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===== 4. Equipment List ===== | ===== 4. Equipment List ===== | ||
==== 4.1. Hardware ==== | ==== 4.1. Hardware ==== | ||
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In addition, we suggest the following instruments: | In addition, we suggest the following instruments: | ||
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==== 4.2. Software ==== | ==== 4.2. Software ==== | ||
The following programs must be installed on your development workstation: | The following programs must be installed on your development workstation: | ||
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* [[http:// | * [[http:// | ||
* [[http:// | * [[http:// | ||
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===== 5. Project Takeaways ===== | ===== 5. Project Takeaways ===== | ||
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- | | + | - Know how to generate a microprocessor development project using MPLAB X. |
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| Evaluation | | Evaluation | ||
- | In all lab exercises of this series, the purposes and requirements will be defined by a problem statement. In most labs, the required hardware is provided on the Basys MX3 trainer board. In some instances, additional hardware | + | In all lab exercises of this series, the purposes and requirements will be defined by a problem statement. In most labs, the required hardware is provided on the Basys MX3 trainer board. In some instances, additional hardware |
Software development will be the focus of the design phase for this series of labs. A significant amount of effort will be needed to understand the required resources of the PIC32MX370 processor along with the functionality of sensors, actuators, displays, and controls used in each lab, as well as the interconnection of these I/O devices to the PICMX370 processor. This includes application specific hardware, interconnection drawings, development tools, and testing instrumentation. Part of processor resource allocation is a table that designates the processor I/O pins and special functions such as timers, communications, | Software development will be the focus of the design phase for this series of labs. A significant amount of effort will be needed to understand the required resources of the PIC32MX370 processor along with the functionality of sensors, actuators, displays, and controls used in each lab, as well as the interconnection of these I/O devices to the PICMX370 processor. This includes application specific hardware, interconnection drawings, development tools, and testing instrumentation. Part of processor resource allocation is a table that designates the processor I/O pins and special functions such as timers, communications, | ||
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//Figure 8.1. Integrated Development Hardware Diagram.// | //Figure 8.1. Integrated Development Hardware Diagram.// | ||
- | The diagram in Fig. 8.1 shows the Basys MX3 unit. The Basys MX3 has a built-in programmer/ | + | The diagram in Fig. 8.1 shows the Basys MX3 unit. The Basys MX3 has a built-in programmer/ |
==== 8.2. General Notes of Interest ==== | ==== 8.2. General Notes of Interest ==== | ||
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#define _SUPPRESS_PLIB_WARNING | #define _SUPPRESS_PLIB_WARNING | ||
#endif | #endif | ||
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- | # | + | #ifndef _DISABLE_OPENADC10_CONFIGPORT_WARNING |
- | #endif | + | # |
+ | #endif | ||
</ | </ | ||
< | < | ||
<ol start=" | <ol start=" | ||
- | < | + | < |
**Table 8.1. XC32 (Global Options) all Options Category.** | **Table 8.1. XC32 (Global Options) all Options Category.** | ||
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< | < | ||
<ol start=" | <ol start=" | ||
- | < | + | < |
==== 8.3. Microcontroller Resources ==== | ==== 8.3. Microcontroller Resources ==== | ||
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- Right-click on the Header Files and select “New” -> “XC32 Header.h”. Name this file “config_bits.h”. | - Right-click on the Header Files and select “New” -> “XC32 Header.h”. Name this file “config_bits.h”. | ||
- Click on “Windows” -> “PIC Memory Views” -> “Configuration Bits”. | - Click on “Windows” -> “PIC Memory Views” -> “Configuration Bits”. | ||
- | - Set the options as shown in Listing | + | - Set the options as shown in Listing |
- Click on “Generate Source Code to Output”. | - Click on “Generate Source Code to Output”. | ||
- Enter “CTRL A” to highlight the text in the output window and “CTRL C” to copy the text. | - Enter “CTRL A” to highlight the text in the output window and “CTRL C” to copy the text. | ||
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==== Listing A.1. Format of a Typical Main Function ==== | ==== Listing A.1. Format of a Typical Main Function ==== | ||
< | < | ||
- | int main(int argc, char** argv) | + | int main(int argc, char** argv) |
{ | { | ||
// Initialization code goes here | // Initialization code goes here | ||
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---- | ---- | ||
- | ===== Appendix C: Basys MX3A Hardware Initialization ===== | + | ===== Appendix C: Basys MX3 Hardware Initialization ===== |
- | Listings C.1 and C.2 that are provided below initialize the Basys MX3 hardware inputs. Development time will be reduced by including these two files in future projects. The hardware.h header file contains an extensive use of macro instructions. Macro instructions are text replacement compiler directives that can result in better documentation and all but eliminate [[http:// | + | Listings C.1 and C.2 that are provided below initialize the Basys MX3 hardware inputs. Development time will be reduced by including these two files in future projects. The hardware.h header file contains an extensive use of macro instructions. Macro instructions are text replacement compiler directives that can result in better documentation and all but eliminate [[http:// |
==== Listing C.1. Hardware Initialization Header File ==== | ==== Listing C.1. Hardware Initialization Header File ==== | ||
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/* Comment out the following define statement when programmer is NOT used to | /* Comment out the following define statement when programmer is NOT used to | ||
* allow using BTNL and BTNU as user inputs. */ | * allow using BTNL and BTNU as user inputs. */ | ||
- | # | + | # |
/* This included file provides access to the peripheral library functions and | /* This included file provides access to the peripheral library functions and | ||
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# | # | ||
- | /* The following macro instruction | + | /* The following macro instruction |
# | # | ||
Set_SW3_in(); | Set_SW3_in(); | ||
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@File Name | @File Name | ||
- | PICmx370.c | + | hardware.c |
| | ||
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#include " | #include " | ||
- | #include " | ||
#include < | #include < | ||
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} /* End of hardware_setup */ | } /* End of hardware_setup */ | ||
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{{ : | {{ : | ||
- | //Figure D.1. Simplified block diagram for a PIC32 I/O pin.(([[http:// | + | //Figure D.1. Simplified block diagram for a PIC32 I/O pin, adapted from figure 12-1 in the PIC32 family data sheet.(([[http:// |
Minimally, the TRIS registers must be set to configure a processor I/O pin as an input or output by setting the bit in the register to 0 for output or 1 for input. By default, all pins that can serve as an analog input are configured to be so. Any analog input pin that is to be used for digital I/O must also be designated to be a digital I/O pin by clearing the appropriate analog select pin. The PIC32MX370 processor has five registers that are used to designate dual-functioning pins as digital or analog inputs. For example, the instruction to clear the analog select pin for PORT D bit 1 (RD1) is “ANSELDbits.ANSD1 = 0;". | Minimally, the TRIS registers must be set to configure a processor I/O pin as an input or output by setting the bit in the register to 0 for output or 1 for input. By default, all pins that can serve as an analog input are configured to be so. Any analog input pin that is to be used for digital I/O must also be designated to be a digital I/O pin by clearing the appropriate analog select pin. The PIC32MX370 processor has five registers that are used to designate dual-functioning pins as digital or analog inputs. For example, the instruction to clear the analog select pin for PORT D bit 1 (RD1) is “ANSELDbits.ANSD1 = 0;". | ||
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If the bit in the TRIS register is set low to make the I/O pin to function as an output, the voltage pin can be set high by writing a 1 to the appropriate bit in the LAT register. Setting the LAT register bit to a zero sets the output pin low (0V). The actual voltage at the output pin depends on the setting in the ODC register. The default configuration has all bits in the ODC register set to zero, which means the output can both source (supply output current) and sink (pull outputs low) current. If the bit in the ODC register is set high, then the output pin functions as open drain, which can sink current but not source current. | If the bit in the TRIS register is set low to make the I/O pin to function as an output, the voltage pin can be set high by writing a 1 to the appropriate bit in the LAT register. Setting the LAT register bit to a zero sets the output pin low (0V). The actual voltage at the output pin depends on the setting in the ODC register. The default configuration has all bits in the ODC register set to zero, which means the output can both source (supply output current) and sink (pull outputs low) current. If the bit in the ODC register is set high, then the output pin functions as open drain, which can sink current but not source current. | ||
- | The maximum current capability of each conventional I/O pin is 15mA (sink or source), while the combined current of all I/O pins is 200mA subject to total power constraints. I/O pins have both open drain and active source output capability. The open drain capability provided by the ODC register is useful when interfacing with switch array keypads (see [[http://store.digilentinc.com/pmodkypd-16-button-keypad/ | + | The maximum current capability of each conventional I/O pin is 15mA (sink or source), while the combined current of all I/O pins is 200mA subject to total power constraints. I/O pins have both open drain and active source output capability. The open drain capability provided by the ODC register is useful when interfacing with switch array keypads (see [[https://digilent.com/shop/ |
The PORT register allows the state of pin to be read regardless if the pin is configured in the TRIS register to be an input or an output. If the voltage on the pin is above the high input threshold, the PORT bit is read as a logic one. Various processor pins have different thresholds. | The PORT register allows the state of pin to be read regardless if the pin is configured in the TRIS register to be an input or an output. If the voltage on the pin is above the high input threshold, the PORT bit is read as a logic one. Various processor pins have different thresholds. | ||
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{ | { | ||
// Initialization | // Initialization | ||
- | ANSELDbits.ANSD1 = 0; // RD1 set to digital I/O | + | ANSELDbits.ANSD1 = 0; |
- | TRISDbits.TRISD1 = 0; // RD1 set to output | + | TRISDbits.TRISD1 = 0; |
- | TRISDbits.TRISD0 = 1; // RD2 set to input | + | TRISDbits.TRISD0 = 1; |
// loop | // loop | ||
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{ | { | ||
LATDbits.LATD1 = PORTDbits.RD0; | LATDbits.LATD1 = PORTDbits.RD0; | ||
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} | } | ||
</ | </ | ||
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// Initialization | // Initialization | ||
ANSELDCLR = 0x02; // RD1 set to digital I/O | ANSELDCLR = 0x02; // RD1 set to digital I/O | ||
- | TRISDCLR = 0x02; // RD1 set to output | + | TRISDCLR = 0x02; |
TRISDSET = 0x01; // RD0 set to input | TRISDSET = 0x01; // RD0 set to input | ||
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{ | { | ||
if(PORTD & 0x01) // Read RD0 pin | if(PORTD & 0x01) // Read RD0 pin | ||
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else | else | ||
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} | } | ||
</ | </ | ||
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---- | ---- | ||
- | ===== Appendix E: PIC32MX370F512L Processor Pin Assignments for Basys MX3A ===== | + | ===== Appendix E: PIC32MX370F512L Processor Pin Assignments for Basys MX3 ===== |
**Table E.1**. Processor IO Assignments. | **Table E.1**. Processor IO Assignments. | ||
^ CPU pin ^ Port ^ ALT ^ Function | ^ CPU pin ^ Port ^ ALT ^ Function | ||
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| 84 | RD7 | RPD7/ | | 84 | RD7 | RPD7/ | ||
| 80 | RD13 | RPD13/ | | 80 | RD13 | RPD13/ | ||
- | | 95 | RG14 | TRD2/RD14 | CP | " | + | | 95 | RG14 | TRD2/RG14 | CP | " |
| 93 | RE0 | PMD0/ | | 93 | RE0 | PMD0/ | ||
| 94 | RE1 | PMD1/ | | 94 | RE1 | PMD1/ | ||
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| 77 | RD2 | AN25/ | | 77 | RD2 | AN25/ | ||
| 88 | RF1 | RPF1/ | | 88 | RF1 | RPF1/ | ||
- | | 25 | RB0 | PGED1/ | + | | 25 | RB0 | PGED1/ |
- | | 24 | RB1 | PGC1/ | + | | 24 | RB1 | PGC1/ |
| 57 | RG2 | SCL1/ | | 57 | RG2 | SCL1/ | ||
| 56 | RG3 | SDA1/ | | 56 | RG3 | SDA1/ | ||
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---- | ---- | ||
+ | [[{}/ | ||
+ | [[{}/ | ||
+ | [[{}learn/ | ||
{{tag> | {{tag> |