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basys3:refmanual [2015/03/04 00:03] – [Software--The first Vivado Design Suite Exclusive:] brandon marcumbasys3:refmanual [2022/03/28 21:51] (current) – Update xilinx links Arthur Brown
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 ===== Overview ===== ===== Overview =====
    
-The Basys3 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity FPGA (Xilinx part number XC7A35T-1CPG236C [[http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf]]), low overall cost, and collection of USB, VGA, and other ports, the Basys3 can host designs ranging from introductory combinational circuits to complex sequential circuits like embedded processors and controllers. It includes enough switches, LEDs and other I/O devices to allow a large number designs to be completed without the need for any additional hardware, and enough uncommitted FPGA I/O pins to allow designs to be expanded using Digilent Pmods or other custom boards and circuits.+The Basys3 board is a complete, ready-to-use digital circuit development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. With its high-capacity FPGA (Xilinx part number XC7A35T-1CPG236C [[https://docs.xilinx.com/v/u/en-US/ds181_Artix_7_Data_Sheet]]), low overall cost, and collection of USB, VGA, and other ports, the Basys3 can host designs ranging from introductory combinational circuits to complex sequential circuits like embedded processors and controllers. It includes enough switches, LEDs and other I/O devices to allow a large number designs to be completed without the need for any additional hardware, and enough uncommitted FPGA I/O pins to allow designs to be expanded using Digilent Pmods or other custom boards and circuits.
  
  
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   * 5 user pushbuttons   * 5 user pushbuttons
   * 4-digit 7-segment display    * 4-digit 7-segment display
-  * Three Pmod connectors +  * Three Pmod ports
   * Pmod for XADC signals   * Pmod for XADC signals
   * 12-bit VGA output    * 12-bit VGA output
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 {{ :basys3-powerblockdiagram.png?nolink |}} {{ :basys3-powerblockdiagram.png?nolink |}}
  
-The Basys3 board can receive power from the Digilent USB-JTAG port (J4) or from a 5 volt external power supply (not included). Jumper JP3 (near the power switch) determines which source is used. +The Basys3 board can receive power from the Digilent USB-JTAG port (J4) or from a 5 volt external power supply (not included). Jumper JP2 (near the power switch) determines which source is used. 
  
  
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 ==== Oscillators/ Clocks ==== ==== Oscillators/ Clocks ====
  
-The Basys3 board includes a single 100MHz oscillator connected to pin W5 (W5 is a MRCC input on bank 34). The input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 100MHz input clock. For a full description of these rules and of the capabilities of the Artix-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx [[http://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf]].+The Basys3 board includes a single 100MHz oscillator connected to pin W5 (W5 is a MRCC input on bank 34). The input clock can drive MMCMs or PLLs to generate clocks of various frequencies and with known phase relationships that may be needed throughout a design. Some rules restrict which MMCMs and PLLs may be driven by the 100MHz input clock. For a full description of these rules and of the capabilities of the Artix-7 clocking resources, refer to the “7 Series FPGAs Clocking Resources User Guide” available from Xilinx [[https://docs.xilinx.com/v/u/en-US/ug472_7Series_Clocking]].
  
 Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard properly instantiates the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The Clocking Wizard can be accessed from within IP Catalog, which can be found under the Project Manager section of the Flow Navigator in Vivado.  Xilinx offers the Clocking Wizard IP core to help users generate the different clocks required for a specific design. This wizard properly instantiates the needed MMCMs and PLLs based on the desired frequencies and phase relationships specified by the user. The wizard will then output an easy to use wrapper component around these clocking resources that can be inserted into the user’s design. The Clocking Wizard can be accessed from within IP Catalog, which can be found under the Project Manager section of the Flow Navigator in Vivado. 
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-====Pmod Connectors ====+====Pmod Ports ====
  
 {{ :basys3_pmod_connectors.png?nolink |}} {{ :basys3_pmod_connectors.png?nolink |}}
  
-A major change from the Basys2 to the Basys3 is the addition of double row Pmod Connectors.  + 
-Digilent produces a large collection of Pmod (Peripheral Module) accessory boards that can attach to the expantion connectors to add ready-made functions such as A/D's, D/A's, motor drivers, sensors, displays, and many other functions. These ports can be used as simple expansion ports, since all of the pin-outs correspond to pins on the FPGA. +A major change from the Basys2 to the Basys3 is the addition of double row Pmod ports.  
 +Digilent produces a large collection of Pmod (Peripheral Module) accessory boards that can attach to the expansion ports to add ready-made functions such as A/D's, D/A's, motor drivers, sensors, displays, and many other functions. These ports can be used as simple expansion ports, since all of the pin-outs correspond to pins on the FPGA. 
  
 {{ :basys3-pmod_connector.png?nolink |}} {{ :basys3-pmod_connector.png?nolink |}}
  
-The Pmod connectors are arranged in a 2x6 right-angle, and are 100-mil female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod connector provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig 20. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching. Pin assignments for the Pmod I/O connected to the FPGA are shown in the below table. +The Pmod ports are arranged in a 2x6 right-angle, and are 100-mil female connectors that mate with standard 2x6 pin headers. Each 12-pin Pmod ports provides two 3.3V VCC signals (pins 6 and 12), two Ground signals (pins 5 and 11), and eight logic signals, as shown in Fig 20. The VCC and Ground pins can deliver up to 1A of current. Pmod data signals are not matched pairs, and they are routed using best-available tracks without impedance control or delay matching. Pin assignments for the Pmod I/O connected to the FPGA are shown in the below table. 
  
-^ Pmod JA   ^ Pmod JB    ^ Pmod JC    ^ Pmod XDAC    ^+^ Pmod JA   ^ Pmod JB    ^ Pmod JC    ^ Pmod JXADC    ^
 | JA1: J1   | JB1: A14   | JC1: K17   | JXADC1: J3   | | JA1: J1   | JB1: A14   | JC1: K17   | JXADC1: J3   |
 | JA2: L2   | JB2: A16   | JC2: M18   | JXADC2: L3   | | JA2: L2   | JB2: A16   | JC2: M18   | JXADC2: L3   |
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 | JA10: G3  | JB10: C16  | JC10: R18  | JXADC10: N1  | | JA10: G3  | JB10: C16  | JC10: R18  | JXADC10: N1  |
  
-:!://The signals in the table correspond to physical pins on the FPGA. These are used to create the net names for the FPGA. These should be available in the XDC file in Vivaddo.// +:!://The signals in the table correspond to physical pins on the FPGA. These are used to create the net names for the FPGA. These should be available in the XDC file in Vivado.//  
 + 
  
-{{ :basys3-pmodpinoutdiagram.png?nolink |}}+{{ :basys3:basys3-pinout.png?nolink |}}
  
 ---- ----
  
-=== Dual Analog/Digital Pmod (JAXC) ===+=== Dual Analog/Digital Pmod (JXADC) ===
  
-{{:basys3-pmodjaxc.png?nolink&300 |}} The on-board Pmod expansion connector labeled “JXADC” is wired to the auxiliary analog input pins of the FPGA. Depending on the configuration, this connector can be used to input differential analog signals to the analog-to-digital converter inside the Artix-7 (XADC). Any or all pairs in the connector can be configured either as analog input or digital input-output. +{{:basys3-pmodjaxc.png?nolink&300 |}} The on-board Pmod expansion port labeled “JXADC” is wired to the auxiliary analog input pins of the FPGA. Depending on the configuration, this port can be used to input differential analog signals to the analog-to-digital converter inside the Artix-7 (XADC). Any or all pairs in the port can be configured either as analog input or digital input-output. 
 The Dual Analog/Digital Pmod on the Basys3 differs from the rest in the routing of its traces. The eight data signals are grouped into four pairs, with the pairs routed closely coupled for better analog noise immunity. Furthermore, each pair has a partially loaded anti-alias filter laid out on the PCB. The filter does not have capacitors C33-C36. In designs where such filters are desired, the capacitors can be manually loaded by the user. The Dual Analog/Digital Pmod on the Basys3 differs from the rest in the routing of its traces. The eight data signals are grouped into four pairs, with the pairs routed closely coupled for better analog noise immunity. Furthermore, each pair has a partially loaded anti-alias filter laid out on the PCB. The filter does not have capacitors C33-C36. In designs where such filters are desired, the capacitors can be manually loaded by the user.
  
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 The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS. The XADC core within the Artix-7 is a dual channel 12-bit analog-to-digital converter capable of operating at 1 MSPS.
  
- Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.”[http://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf + Either channel can be driven by any of the auxiliary analog input pairs connected to the JXADC header. The XADC core is controlled and accessed from a user design via the Dynamic Reconfiguration Port (DRP). The DRP also provides access to voltage monitors that are present on each of the FPGA’s power rails, and a temperature sensor that is internal to the FPGA. For more information on using the XADC core, refer to the Xilinx document titled “7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter.”: [[https://docs.xilinx.com/v/u/en-US/ug480_7Series_XADC]]
-]+