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reference:instrumentation:zmodadc:reference-manual [2019/10/21 11:40] – [4.3. AVCC4V5] Mircea Dabacanreference:instrumentation:zmodadc:reference-manual [2019/10/25 13:29] – [Features] Mircea Dabacan
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   * Channel type: single ended   * Channel type: single ended
   * Resolution: 14-bit   * Resolution: 14-bit
-  * Absolute Resolution (High Gain: ±1V input voltage range): 0.13mV +  * Input range: ±1V (High Gain) or ±25V (Low Gain)  
-  * Absolute Resolution (Low Gain: ±25V input voltage range): 3.17mV +  * Absolute Resolution 0.13mV (High Gain) or 3.21mV (Low Gain)  
-  * Accuracy (High Gain): ±10mV±0.5% FIXME +  * Accuracy ±10mV±0.5% FIXME (High Gain) or ±100mV±0.5% FIXME (Low Gain)
-  * Accuracy (Low Gain): ±100mV±0.5% FIXME+
   * Sample rate (real time): 100MS/s   * Sample rate (real time): 100MS/s
   * Input impedance: 1MΩ||18pF    * Input impedance: 1MΩ||18pF 
   * Analog bandwidth: 70 MHz+ @ 3dB, 30 MHz @ 0.5dB, 20 MHz @ 0.1dB   * Analog bandwidth: 70 MHz+ @ 3dB, 30 MHz @ 0.5dB, 20 MHz @ 0.1dB
-  * Input range: ±25V 
   * Input protected to: ±50V   * Input protected to: ±50V
    
- 
- 
 ===== 1. Architectural Overview and Block Diagram ===== ===== 1. Architectural Overview and Block Diagram =====
  
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 Zmod ADC's  block diagram is presented in [[reference:instrumentation:zmodadc:reference-manual#figure_2|Fig. 2]] below. The core of the Analog Zmod ADC is the dual channel, high speed, low power, 14-bit, 105MS/s ADC, [[https://www.analog.com/en/products/ad9648.html|AD9648]]. The carrier board is responsible to configure the internal registers of the ADC circuit, provide the acquisition clock and receive the data. Zmod ADC's  block diagram is presented in [[reference:instrumentation:zmodadc:reference-manual#figure_2|Fig. 2]] below. The core of the Analog Zmod ADC is the dual channel, high speed, low power, 14-bit, 105MS/s ADC, [[https://www.analog.com/en/products/ad9648.html|AD9648]]. The carrier board is responsible to configure the internal registers of the ADC circuit, provide the acquisition clock and receive the data.
  
-The **Analog Input** block is also called the **Scope**, because of similar structure and behavior to such a front end. The signals in this circuitry use a "SC" indexes to indicate they are related to the scope block. Signal and equations also use certain naming conventions. Analog voltages are prefixed with a "V" (for voltage), and suffixes and indexes are used in various ways: to specify the location in the signal path (IN, MUX, BUF, ADC, etc.); to indicate the related instrument (SC, etc.); to indicate the channel (1 or 2); and to indicate the type of signal (P, N, or diff). Referring to the block diagram in [[reference:instrumentation:zmodadc:reference-manual#figure_2|Fig. 2]] below:+The **Analog Input** block is also called the **Scope**, because of similar structure and behavior to such a front end. The signals in this circuitry use a "SC" indexes to indicate they are related to the scope block. Signals and equations also use certain naming conventions. Analog voltages are prefixed with a "V" (for voltage), and suffixes and indexes are used in various ways: to specify the location in the signal path (IN, MUX, BUF, ADC, etc.); to indicate the related instrument (SC, etc.); to indicate the channel (1 or 2); and to indicate the type of signal (P, N, or diff). Referring to the block diagram in [[reference:instrumentation:zmodadc:reference-manual#figure_2|Fig. 2]] below:
  
   * The** Analog Inputs/Scope** instrument block includes:   * The** Analog Inputs/Scope** instrument block includes:
      * **Input Divider and Gain Selection**: high bandwidth input adapter/divider. High or low-gain can be selected by the FPGA      * **Input Divider and Gain Selection**: high bandwidth input adapter/divider. High or low-gain can be selected by the FPGA
      * **Buffer**: high impedance buffer      * **Buffer**: high impedance buffer
-     * **Driver**: provides appropriate signal levels and protection to the ADC. Offset voltage is added for vertical position setting+     * **Driver**: provides appropriate signal levels and protection to the ADC. 
      * **Scope Reference**: generates and buffers reference voltages for the scope stages      * **Scope Reference**: generates and buffers reference voltages for the scope stages
      * **ADC**: the analog-to-digital converter for both scope channels.      * **ADC**: the analog-to-digital converter for both scope channels.
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      * The **Calibration Memory** stores all calibration parameters. Except for the “Probe Calibration” trimmers in the scope Input divider, the Zmod ADC includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The application software uses these parameters to correct the acquired data and the generated signals      * The **Calibration Memory** stores all calibration parameters. Except for the “Probe Calibration” trimmers in the scope Input divider, the Zmod ADC includes no analog calibration circuitry. Instead, a calibration operation is performed at manufacturing (or by the user), and parameters are stored in memory. The application software uses these parameters to correct the acquired data and the generated signals
  
-In the sections that follow, schematics are not shown separately for identical blocks.  For example, the Scope Input Divider and Gain Selection schematic is only shown for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As examples, in equation \ref{4} below, $V_{in diff}$ does not contain the instrument index (which by context is understood to be the Scope), nor the channel index (because the equation applies to both channels 1 and 2). In equation \ref{3}, the type index is also missing because $V_{mux}$ and $V_{in}$ refer to any of //P// (positive), //N// (negative) or //diff// (differential) values.+In the sections that follow, schematics are not shown separately for identical blocks.  For example, the Scope Input Divider and Gain Selection schematic is only shown for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As examples, in equation \ref{1} below, $V_{SCOPE-SMA}$ does not contain the channel index (because the equation applies to both channels 1 and 2). 
  
 {{:reference/instrumentation/zmodadc/zmodadcblockdiagram.png?w=600&h=400&t=1566215726&tok=f0af6e}} {{:reference/instrumentation/zmodadc/zmodadcblockdiagram.png?w=600&h=400&t=1566215726&tok=f0af6e}}
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 $$-50V<V_{SCOPE-SMA}<50V\label{1}\tag{1}$$ $$-50V<V_{SCOPE-SMA}<50V\label{1}\tag{1}$$
  
-The DC low gain is: $$\frac {V_{SC-LG}}{V_{SCOPE-SMA}}=\frac {R_5}{R_1+R_3+R_5}=0.04\label{3}\tag{3}$$+The DC low gain is: $$\frac {V_{SC-LG}}{V_{SCOPE-SMA}}=\frac {R_5}{R_1+R_3+R_5}=0.04\label{2}\tag{2}$$
  
-The low gain is used for input voltages: $$-25V \le V_{SCOPE-SMA}  \le 25V\label{4}\tag{4}$$+The low gain range: $$-25V \le V_{SCOPE-SMA}  \le 25V\label{3}\tag{3}$$
  
-The high gain is: $$\frac {V_{SC-HG}}{V_{SCOPE-SMA}} = \frac {R_4 + R_6}{R_2 + R_4 + R_6} = 0.993 \label{5}\tag{5}$$+The high gain is: $$\frac {V_{SC-HG}}{V_{SCOPE-SMA}} = \frac {R_4 + R_6}{R_2 + R_4 + R_6} = 0.96 \label{4}\tag{4}$$
  
-The high gain is used for input voltages: $$-1V \le V_{SCOPE-SMA} \le 1V \label{6}\tag{6}$$+The high gain range: $$-1V \le V_{SCOPE-SMA} \le 1V \label{5}\tag{5}$$
  
 The two dividers are designed to have the same equivalent impedance (both active and reactive):  The two dividers are designed to have the same equivalent impedance (both active and reactive): 
  
-$$R_{ech} = R_1 + R_3 + R_4 = R_2 + R_4 + R_6 = 1Mohm\label{7}\tag{7}$$+$$R_{ech} = R_1 + R_3 + R_5 = R_2 + R_4 + R_6 = 1Mohm\label{6}\tag{6}$$
  
 Experiments shown that there are significant parasitic capacities of the layout and buffer input stage: C<sub>PH</sub> (high gain divider), parallel to C<sub>6</sub>, and C<sub>PL</sub> (low gain divider), parallel to C<sub>7</sub>. The trimmers should compensate for these parasitic capacities and adjust for perfect matching: Experiments shown that there are significant parasitic capacities of the layout and buffer input stage: C<sub>PH</sub> (high gain divider), parallel to C<sub>6</sub>, and C<sub>PL</sub> (low gain divider), parallel to C<sub>7</sub>. The trimmers should compensate for these parasitic capacities and adjust for perfect matching:
  
-$$C_3*R_2 = (C_{PH} + C_6)*(R_4+R_6)\label{8}\tag{8}$$ +$$C_3*R_2 = (C_{PH} + C_6)*(R_4+R_6)\label{7}\tag{7}$$ 
-$$(C_{PH} + C_6) = \frac{C_3*R_2}{R_4+R_6} = 18pF\label{9}\tag{9}$$+$$(C_{PH} + C_6) = \frac{C_3*R_2}{R_4+R_6} = 18pF\label{8}\tag{8}$$
  
-$$(C_4 + C_5)*(R_1 + R_3) = (C_{PL} + C_7)*R_5\label{10}\tag{10}$$ +$$(C_4 + C_5)*(R_1 + R_3) = (C_{PL} + C_7)*R_5\label{9}\tag{9}$$ 
-$$(C_{PL} + C_7) = (C_4 + C_5)*\frac{(R_1 + R_3)}{R_5}\label{11}\tag{11}$$+$$(C_{PL} + C_7) = (C_4 + C_5)*\frac{(R_1 + R_3)}{R_5}\label{10}\tag{10}$$
  
 With the chosen values, the correct adjustment results in about mid-position of trimmers C<sub>5</sub> and C<sub>6</sub>: With the chosen values, the correct adjustment results in about mid-position of trimmers C<sub>5</sub> and C<sub>6</sub>:
  
-$$C_5 = C_6 = 7pF\label{12}\tag{12}$$+$$C_5 = C_6 = 7pF\label{11}\tag{11}$$
  
 which solves the parasitic capacities as: which solves the parasitic capacities as:
  
-$$C_{PH} = 11pF\label{13}\tag{13}$$ +$$C_{PH} = 11pF\label{12}\tag{12}$$ 
-$$C_{PL} = 8.8pF\label{14}\tag{14}$$+$$C_{PL} = 8.8pF\label{13}\tag{13}$$
  
 The Low Gain and High Gain dividers have very close equivalent capacitance, within the tolerances and model approximations: The Low Gain and High Gain dividers have very close equivalent capacitance, within the tolerances and model approximations:
  
-$$C_{HGech} = \frac{C_3*R_2}{R_2+R_4+R_6} = C_{ech} = 17.28pF\label{15}\tag{15}$$ +$$C_{HGech} = \frac{C_3*R_2}{R_2+R_4+R_6} = C_{ech} = 17.28pF\label{14}\tag{14}$$ 
-$$C_{LGech} = \frac{(C_7+C_{PL})*R_5}{R_1+R_3+R_5} = 16.03p\label{16}\tag{16}$$+$$C_{LGech} = \frac{(C_7+C_{PL})*R_5}{R_1+R_3+R_5} = 16.03p\label{15}\tag{15}$$
  
 Experiments show that the equivalent capacitances are even closer than the values above, about 18pF. The computing error mainly derives from trimmer position approximation.   Experiments show that the equivalent capacitances are even closer than the values above, about 18pF. The computing error mainly derives from trimmer position approximation.  
 +
 +$$C_{ech} = 18p\label{16}\tag{16}$$
  
 The IC2 relay shorts the C1 capacitor when DC coupling is desired. Otherwise, C1 forms a High Pass filter with the selected divider, for AC coupling, with the corner frequency: The IC2 relay shorts the C1 capacitor when DC coupling is desired. Otherwise, C1 forms a High Pass filter with the selected divider, for AC coupling, with the corner frequency:
  
-$$f_c = \frac{1}{2*\pi*R_{ech}*(C_{ech}+C_{in})} \approx \frac{1}{2*\pi*R_{ech}*C_{ech}} = 10Hz\label{17}\tag{17}$$+$$f_c = \frac{1}{2*\pi*R_{ech}*(C_{ech}+C_{1})} \approx \frac{1}{2*\pi*R_{ech}*C_{1}} = 10.6Hz\label{17}\tag{17}$$
  
 {{:reference:instrumentation:zmodadc:inputdivider.png}}  {{:reference:instrumentation:zmodadc:inputdivider.png}} 
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 ==== 2.2. Scope Buffer ==== ==== 2.2. Scope Buffer ====
  
-A non-inverting [[https://www.analog.com/en/products/ada4817-1.html|ADA4817]] stage provides very high impedance as load for the input divider [[reference:instrumentation:zmodadc:reference-manual#figure_6|Fig. 6]]. +A non-inverting [[https://www.analog.com/en/products/ada4817-1.html|ADA4817]] stage provides very high impedance as load for the input divider. 
  
   * High speed   * High speed
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   * Supply quiescent current per amplifier: 19 mAtypical   * Supply quiescent current per amplifier: 19 mAtypical
   * Powered down supply quiescent current per amplifier: 1.5 mAtypical   * Powered down supply quiescent current per amplifier: 1.5 mAtypical
- 
-D1 protects the opAmp over-voltage. 
- 
  
 {{:reference:instrumentation:zmodadc:buffer.png?w=450}} {{:reference:instrumentation:zmodadc:bufferSup.png?w=700&h=350&}}  {{:reference:instrumentation:zmodadc:buffer.png?w=450}} {{:reference:instrumentation:zmodadc:bufferSup.png?w=700&h=350&}} 
 //{{anchor:figure_6:Figure 6. Buffer.}}// //{{anchor:figure_6:Figure 6. Buffer.}}//
- 
-Resistors and capacitors in the figure might reduce peaking (which might be significant at unity gain). 
  
 The [[https://www.analog.com/en/products/ada4817-1.html|ADA4817]] is supplied +4.5V/-2.5V.  The [[https://www.analog.com/en/products/ada4817-1.html|ADA4817]] is supplied +4.5V/-2.5V. 
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 The actual input and output range (for nominal usage) is: $-1V<V_{SC-HLG}=V_{BUFF}<1V\label{21}\tag{21}$ The actual input and output range (for nominal usage) is: $-1V<V_{SC-HLG}=V_{BUFF}<1V\label{21}\tag{21}$
  
-The Zmod ADC is specified to resist to accidental input voltages up to +/-50V. In these cases, the buffer input voltage is limited by D1 at 0.6V above the AVCC4V5 or below AVCC-2V5, upon accidental voltage polarity. The D1 current is limited by R2 (at High Gain) or R1+R3 (at Low Gain) (see the input divider schematic). The worse case is V<sub>SCOPE_SMA</sub>=-50V on High Gain scale:+The [[https://www.analog.com/en/products/ada4817-1.html|ADA4817]] data sheet does not include any explicit or implicit mention of input protection diodes, nor about the maximum current supported by such diodes, so external D1 was added in the schematic for safety. However, the leakage current of D1 adds significant error and experiments proved that the input protection diodes do exist within the [[https://www.analog.com/en/products/ada4817-1.html|ADA4817]], so D1 is a "No Load".  
  
-$$I_{D1}=\frac{V_{SCOPE-SMA}-V_{AVCC-2V5}}{R_2}=\frac{-50V+2.5V}{40.2kohm}=-1.18mA\label{22}\tag{22}$$ +The Zmod ADC is specified to resist to accidental input voltages up to +/-50V. In these cases, the buffer input voltage is limited by the protection diodes at 0.6V above the AVCC4V5 or below AVCC-2V5. The protection current is limited by R2 (at High Gain) or R1+R3 (at Low Gain) (see the input divider schematic). The worse case is V<sub>SCOPE_SMA</sub>=-50V on High Gain scale:
- +
-The [[https://www.analog.com/en/products/ada4817-1.html|ADA4817]] data sheet does not include any explicit or implicit mention of input protection diodes, nor about the maximum current supported by such diodes, so external D1 was added in the schematic for safety. +
  
 +$$I_{+}=\frac{V_{SCOPE-SMA}-V_{AVCC-2V5}}{R_2}=\frac{-50V+2.5V}{40.2kohm}=-1.18mA\label{22}\tag{22}$$
  
 ==== 2.3. Scope Reference ==== ==== 2.3. Scope Reference ====
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 $$V_{REFADC}=V_{REF1V2SC}*\frac {R_{73}}{R_{71}+R_{73}}=1V\label{23}\tag{23}$$ $$V_{REFADC}=V_{REF1V2SC}*\frac {R_{73}}{R_{71}+R_{73}}=1V\label{23}\tag{23}$$
  
-Another [[https://www.analog.com/en/products/ada4841-2.html|ADA4841-2]] OpAmp buffers the VCM voltage generated by the ADC to feed the ADC buffer, in [[reference:instrumentation:zmodadc:reference-manual#figure_8|Fig. 8]].+An [[https://www.analog.com/en/products/ada4841-2.html|ADA4841-2]] OpAmp buffers the VCM voltage generated by the ADC to feed the ADC buffer, in [[reference:instrumentation:zmodadc:reference-manual#figure_8|Fig. 8]].
  
 [[https://www.analog.com/en/products/ada4841-2.html|ADA4841-2]]: [[https://www.analog.com/en/products/ada4841-2.html|ADA4841-2]]:
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 $$V_{CMSC}=V_{VCMADC}=V_{VCMADC0V9}*(1+\frac {R_{65}}{R_{70}})=1.2V\label{24}\tag{24}$$ $$V_{CMSC}=V_{VCMADC}=V_{VCMADC0V9}*(1+\frac {R_{65}}{R_{70}})=1.2V\label{24}\tag{24}$$
  
-An [[https://www.analog.com/en/products/lt1461.html|LT1461-2.5]] reference generates a voltage used for rising the input common mode voltage of the ADC buffer, in [[reference:instrumentation:zmodadc:reference-manual#figure_9|Fig. 9]]. +An [[https://www.analog.com/en/products/lt1461.html|LT1461-2.5]] reference generates a voltage used for rising the input common mode voltage of the ADC buffer, in [[reference:instrumentation:zmodadc:reference-manual#figure_10|Fig. 10]]. 
  
 [[https://www.analog.com/en/products/lt1461.html|LT1461-2.5]]: [[https://www.analog.com/en/products/lt1461.html|LT1461-2.5]]:
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 ==== 2.4. Scope Driver ==== ==== 2.4. Scope Driver ====
  
-IC2, [[https://www.analog.com/en/products/ltc6406.html|LTC6406]], in [[reference:instrumentation:zmodadc:reference-manual#figure_8|Fig. 8]] is the ADC dirver.+IC2, [[https://www.analog.com/en/products/ltc6406.html|LTC6406]], in [[reference:instrumentation:zmodadc:reference-manual#figure_10|Fig. 10]] is the ADC dirver.
  
   * Low Noise: 1.6nV/√Hz RTI   * Low Noise: 1.6nV/√Hz RTI
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 The nominal differential ADC input voltage range is: The nominal differential ADC input voltage range is:
  
-$$-0.947V<V_{ADC\;diff}<0.947V\label{33}\tag{33}$$+$$-1V<V_{ADC\;diff}<1V\label{33}\tag{33}$$
  
 The output divider common mode voltage is close to the recommended 0.9V: The output divider common mode voltage is close to the recommended 0.9V:
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 $$V_{CMADC}=(V_{ADCP}+V_{ADCN})/2=0.895V\label{34}\tag{34}$$ $$V_{CMADC}=(V_{ADCP}+V_{ADCN})/2=0.895V\label{34}\tag{34}$$
  
-The nominal ADC input single ended voltage range is:+The ADC input single ended voltage range is:
  
-$$0.421V<V_{ADCP},V_{ADCN}<1.369V\label{35}\tag{35}$$+$$0.395V<V_{ADCP},V_{ADCN}<1.395V\label{35}\tag{35}$$
  
-For the ADC input protection, the maximum driver single ended voltage should be considered. The data sheet does not specify the worst case (saturated output), but only the nominal one (warrantied linear). Based on the data sheet and measurements, the driver maximum saturated single ended voltage was estimated to:+For the ADC input protection, the maximum driver single ended voltage should be considered. The driver amplifier datasheet only specifies the linear output voltage range. There is no information about the worst case saturated output voltages. Based on the data sheet and measurements, the driver maximum saturated single ended voltage was estimated to:
  
 $$V_{OUT\;max\;sat}<2.5V\label{36}\tag{36}$$ $$V_{OUT\;max\;sat}<2.5V\label{36}\tag{36}$$
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 $$V_{ADC\;max\;sat}=V_{OUT\;max\;sat}*G_{div}=1.865V\label{37}\tag{37}$$ $$V_{ADC\;max\;sat}=V_{OUT\;max\;sat}*G_{div}=1.865V\label{37}\tag{37}$$
  
-which is less than the allowed voltage at the ADC input = 2V. +which is less than the allowed voltage at the ADC input = 2.1V. 
  
 ---- ----
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 ==== 2.5. Scope ADC ==== ==== 2.5. Scope ADC ====
  
-The Zmod ADC uses a dual channel, high speed, low power, 14-bit, 105MS/s ADC (Analog part number [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9648/products/product.html|AD9648]]), as shown in [[reference:instrumentation:zmodadc:reference-manual#figure_9|Fig. 9]].+The Zmod ADC uses a dual channel, high speed, low power, 14-bit, 105MS/s ADC (Analog part number [[http://www.analog.com/en/analog-to-digital-converters/ad-converters/ad9648/products/product.html|AD9648]]), as shown in [[reference:instrumentation:zmodadc:reference-manual#figure_11|Fig. 11]].
  
 {{:reference:instrumentation:zmodadc:ADC.png}}  {{:reference:instrumentation:zmodadc:ADC.png}} 
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   * Data clock out with programmable clock and data alignment   * Data clock out with programmable clock and data alignment
  
-The differential inputs are driven via a low-pass filter comprised of C114 together with R13, R15, R16, R17 in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by four for operating at a constant 100 MHz sampling rate.  The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage.+The differential inputs are driven via a low-pass filter comprised of C114 together with R13, R15, R16, R17 in the buffer stage. The differential clock is AC-coupled and the line is impedance matched. The clock is internally divided by 4 to operate the ADC at a constant 100 MHz sampling rate.  The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage.
  
-The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8V by the SYZYGY™ voltage Vadj.+The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8V by the SYZYGY™ voltage V<sub>adj</sub>.
  
-To minimize the number of used FPGA pins; a multiplexed mode is used, to combine the two channels on a single data bus. CLKOUT_SC is provided to the FPGA for synchronizing data. + The multiplexed mode is used, to combine the two channels on a single data bus and minimize the number of used FPGA pins. CLKOUT_SC is provided to the FPGA for synchronizing data. 
 ---- ----
  
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-Combining Gain equations \ref{3}, \ref{5}, \ref{13}, and \ref{15} from previous chapters, the total scope gains are:+Combining Gain equations \ref{2}, \ref{4}, \ref{20}, \ref{26}, and \ref{27} from previous chapters, the total scope gains are:
  
 $$Low \; gain = \frac{V_{ADC\;diff}}{V_{SCOPE-SMA}}=0.038\label{38}\tag{38}$$ $$Low \; gain = \frac{V_{ADC\;diff}}{V_{SCOPE-SMA}}=0.038\label{38}\tag{38}$$
-$$High \; gain = \frac{V_{ADC\;diff}}{V_{SCOPE-SMA}}=0.941\label{39}\tag{39}$$+$$High \; gain = \frac{V_{ADC\;diff}}{V_{SCOPE-SMA}}=0.91\label{39}\tag{39}$$
  
-Considering the ADC input voltage range shown in \ref{18}:+Considering the ADC input voltage range shown in \ref{33}:
  
-$$at \; low \; gain: -26.3V<V_{in\;diff}<26.3V$$ +$$at \; low \; gain: -26.3V<V_{SCOPE-SMA}<26.3V$$ 
-$$at \; high \; gain: -1.06V<V_{in\;diff}<1.06V\label{40}\tag{40}$$+$$at \; high \; gain: -1.1V<V_{SCOPE-SMA}<1.1V\label{40}\tag{40}$$
  
 To cover component value tolerances and to allow software calibration, only the ranges below are specified. To cover component value tolerances and to allow software calibration, only the ranges below are specified.
  
-$$at \; low \; gain: -25V<V_{in\;diff}<25V\label{41}\tag{41}$$ +$$at \; low \; gain: -25V<V_{SCOPE-SMA}<25V\label{41}\tag{41}$$ 
-$$at \; high \; gain: -1V<V_{in\;diff}<1V\label{42}\tag{42}$$+$$at \; high \; gain: -1V<V_{SCOPE-SMA}<1V\label{42}\tag{42}$$
  
 With the 14-bit ADC, the absolute resolution of the scope is: With the 14-bit ADC, the absolute resolution of the scope is:
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 For V<sub>in</sub> voltage value at the input of the Scope channel, the ZmodADC sends a signed 14 bit integer, N. This value is used to compute V<sub>in</sub>: For V<sub>in</sub> voltage value at the input of the Scope channel, the ZmodADC sends a signed 14 bit integer, N. This value is used to compute V<sub>in</sub>:
  
-$$V_{in} = \frac{N \cdot Gain \cdot (1+CG)}{2^{13}} + CA \label{45}\tag{45}$$+$$V_{in} = \frac{N \cdot Range \cdot (1+CG)}{2^{13}} + CA \label{45}\tag{45}$$
  
 were: were:
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   * CA = calibration Additive constant (for the appropriate channel and gain; see [[reference:instrumentation:zmoddac:reference-manual#Table_3|Table 3]])   * CA = calibration Additive constant (for the appropriate channel and gain; see [[reference:instrumentation:zmoddac:reference-manual#Table_3|Table 3]])
   * CG = calibration Gain constant (for the appropriate channel and gain; see [[reference:instrumentation:zmoddac:reference-manual#Table_3|Table 3]])   * CG = calibration Gain constant (for the appropriate channel and gain; see [[reference:instrumentation:zmoddac:reference-manual#Table_3|Table 3]])
-  * Gain = the ideal gain of the Scope input stage:+  * Range= the ideal Range of the Scope input stage (approximation of the values in equation \ref{40}):
     * 1.086 (for low range: ±1V) or      * 1.086 (for low range: ±1V) or 
     * 26.25 (for high range: ±25V)     * 26.25 (for high range: ±25V)
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 ==== 2.7 Scope Spectral Characteristics ==== ==== 2.7 Scope Spectral Characteristics ====
  
-[[reference:instrumentation:zmodadc:reference-manual#figure_12|Fig. 12]] shows a typical spectral characteristic of the scope input stage. An PXIe-5433 80 MHz Function/Arbitrary Waveform Generator was used to generate the input signal of 0.9V, for High Gain Scale, respectively 10V for the Low Gain scale. A Tektronix DPO5204B scope was used for measuring the reference signal (at the scope SMA connector) and the output signal (at the input of the ADC. A differential probe was used to read the output signal on the pads of the unloaded C115.+[[reference:instrumentation:zmodadc:reference-manual#figure_12|Fig. 12]] shows a typical spectral characteristic of the scope input stage. A PXIe-5433 80 MHz Function/Arbitrary Waveform Generator was used to generate the input signal of 0.9V, for High Gain Scale, respectively 10V for the Low Gain scale. A Tektronix DPO5204B scope was used for measuring the reference signal (at the scope SMA connector) and the output signal (at the input of the ADC). A differential probe was used to read the output signal on the pads of the unloaded C115.
 The signal swept from 800kHz to 80MHz. The effective values of the input and output signals were recorded for each frequency. The measurements were furter processesd to display the input stage frequency characteristics, as shown in [[reference:instrumentation:zmodadc:reference-manual#figure_10|Fig. 10]].  The signal swept from 800kHz to 80MHz. The effective values of the input and output signals were recorded for each frequency. The measurements were furter processesd to display the input stage frequency characteristics, as shown in [[reference:instrumentation:zmodadc:reference-manual#figure_10|Fig. 10]]. 
  
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 ===== 3. MCU ===== ===== 3. MCU =====
  
-The [[https://www.microchip.com/wwwproducts/en/ATTINY44A|ATtinny44]] MCU in [[reference:instrumentation:zmodadc:reference-manual#figure_11|Fig. 11]] works as a <del>SPI</del> memory, storing the SYZYGY™ DNA information and the Calibration Coefficients. The J5 connector is used for programming the MCU and the SYZYGY™ DNA at manufacturing. The memory is read-only and its structure can be consulted below.+The [[https://www.microchip.com/wwwproducts/en/ATTINY44A|ATtinny44]] MCU in [[reference:instrumentation:zmodadc:reference-manual#figure_13|Fig. 13]] works as a I2C memory, storing the SYZYGY™ DNA information and the Calibration Coefficients. The J5 connector is used for programming the MCU and the SYZYGY™ DNA at manufacturing.  
 + 
 +The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as "read-only". The User Calibration Coefficients are stored in the EEPROM memory of the MCU, which is write-protected via a magic number at a magic address. The memory structure can be consulted below.
  
 {{:reference:instrumentation:zmodadc:MCU.png}} {{:reference:instrumentation:zmodadc:MCU.png}}
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 |  0x7080 - 0x70FF   |    Future Use      |   128          |  |  0x7080 - 0x70FF   |    Future Use      |   128          | 
    
-At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C.+At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C. To re-enable the write protection one has to write a any other number to the magic address.
  
 //{{anchor:table_5:Table 5. The Write Protection Disable magic number and address}}// //{{anchor:table_5:Table 5. The Write Protection Disable magic number and address}}//
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 {{:reference:instrumentation:zmodadc:Avcc1V8.png?w=700}} {{:reference:instrumentation:zmodadc:Avcc1V8.png?w=700}}
-//{{anchor:figure_12:Figure 12. AVCC1V8}}//+//{{anchor:figure_14:Figure 14. AVCC1V8}}//
  
 ==== 4.2. AVCC3V0 ==== ==== 4.2. AVCC3V0 ====
  
-The analog supply AVCC3V0 is built from VCC3V3 using IC22, an [[https://www.analog.com/en/products/adp122.html|ADP122]] 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Fixed Output Voltage. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB3 in [[reference:instrumentation:zmodadc:reference-manual#figure_8|Fig. 8]], FB6 (Channel 2 ADC Driver - not shown), FB7 in [[reference:instrumentation:zmodadc:reference-manual#figure_7|Fig. 7]].+The analog supply AVCC3V0 is built from VCC3V3 using IC22, an [[https://www.analog.com/en/products/adp122.html|ADP122]] 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Fixed Output Voltage. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB3 in [[reference:instrumentation:zmodadc:reference-manual#figure_10|Fig. 10]], FB6 (Channel 2 ADC Driver - not shown), FB7 in [[reference:instrumentation:zmodadc:reference-manual#figure_7|Fig. 7]].
  
   * Input voltage supply range: 2.3 V to 5.5 V   * Input voltage supply range: 2.3 V to 5.5 V
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 {{:reference:instrumentation:zmodadc:Avcc3V0.png?w=550}} {{:reference:instrumentation:zmodadc:Avcc3V0.png?w=550}}
-//{{anchor:figure_13:Figure 13. AVCC3V0}}//+//{{anchor:figure_15:Figure 15. AVCC3V0}}//
  
 ==== 4.3. AVCC4V5 ==== ==== 4.3. AVCC4V5 ====
  
-The analog supply AVCC4V5 is built from VCC5V0 using IC19, an [[https://www.analog.com/en/products/adp123.html|ADP123]] 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Adjustable Output Voltage. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB2 in [[reference:instrumentation:zmodadc:reference-manual#figure_6|Fig. 6]], FB5 (Channel 2 ADC Buffer - not shown), FB8 in [[reference:instrumentation:zmodadc:reference-manual#figure_7|Fig. 7]].+The analog supply AVCC4V5 is built from VCC5V0 using IC19, an [[https://www.analog.com/en/products/adp123.html|ADP123]] 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Adjustable Output Voltage. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB2 in [[reference:instrumentation:zmodadc:reference-manual#figure_6|Fig. 6]], FB5 (Channel 2 ADC Buffer - not shown), FB8 in [[reference:instrumentation:zmodadc:reference-manual#figure_9|Fig. 9]].
  
   * Input voltage supply range: 2.3 V to 5.5 V   * Input voltage supply range: 2.3 V to 5.5 V
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 {{:reference:instrumentation:zmodadc:Avcc4V5.png?w=900}} {{:reference:instrumentation:zmodadc:Avcc4V5.png?w=900}}
-//{{anchor:figure_14:Figure 14. AVCC4V5}}//+//{{anchor:figure_16:Figure 16. AVCC4V5}}//
  
 ==== 4.4. AVCC-2V5 ==== ==== 4.4. AVCC-2V5 ====
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   * Available in ultrasmall, 6-lead TSOT package    * Available in ultrasmall, 6-lead TSOT package 
  
-{{:reference:instrumentation:zmodadc:AvccNeg2V5.png}} +{{:reference:instrumentation:zmodadc:AvccNeg2V5.png?w=1000}} 
-//{{anchor:figure_15:Figure 15. AVCC-2V5}}//+//{{anchor:figure_17:Figure 17. AVCC-2V5}}//
  
  
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 {{:reference:instrumentation:zmodadc:SyzygyConn.png}} {{:reference:instrumentation:zmodadc:SyzygyConn.png}}
-//{{anchor:figure_16:Figure 16. SYZYGY™ connector}}//+//{{anchor:figure_18:Figure 18. SYZYGY™ connector}}//
  
 ===== 6. The SYZYGY™ compatibility table ===== ===== 6. The SYZYGY™ compatibility table =====