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programmable-logic:cora-z7:start [2021/10/27 23:32] – Arthur Brown | programmable-logic:cora-z7:start [2023/08/29 23:06] (current) – ↷ Links adapted because of a move operation Arthur Brown | ||
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| Store Page = https:// | | Store Page = https:// | ||
| Manual = [[reference-manual]] | | Manual = [[reference-manual]] | ||
- | | Support = http:// | + | | Support = http:// |
| Title = Cora Z7 | | Title = Cora Z7 | ||
| Subtitle = Zynq for Hobbyists and Makers | | Subtitle = Zynq for Hobbyists and Makers | ||
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| Bullet = Programmable from JTAG and microSD card | | Bullet = Programmable from JTAG and microSD card | ||
| Header = Key FPGA Specifications | | Header = Key FPGA Specifications | ||
- | | Part Number = XC7Z010-1CLG400 \\ (XC7Z007S-1CLG400*) | + | | Part Number = XC7Z007S-1CLG400 \\ (XC7Z010-1CLG400*) |
- | | Logic Slices = 4,400 (3,600*) | + | | Logic Slices = 3,600 (4,400*) |
- | | 6-input LUTs = | + | | 6-input LUTs = 14, |
- | | Flip-Flops = 35,200 (28,800*) | + | | Flip-Flops = 28, |
- | | Block RAM = 270 KB (225 KB*) | + | | Block RAM = 225 KB (270 KB*) |
- | | DSP Slices = 80 (66*) | + | | DSP Slices = 66 (80*) |
| Clock Resources = Zynq PLL with 4 outputs \\ 2 PLLs \\ 2 MMCMs \\ 125 MHz external clock | | Clock Resources = Zynq PLL with 4 outputs \\ 2 PLLs \\ 2 MMCMs \\ 125 MHz external clock | ||
| Internal ADC = Dual-channel, | | Internal ADC = Dual-channel, | ||
- | | Bullet = (*Z7-07S variant value in parentheses where different) | + | | Bullet = (*Z7-10 variant value in parentheses where different) |
| Header = Connectivity and On-board I/O | | Header = Connectivity and On-board I/O | ||
| USB = USB-UART \\ USB-JTAG Programmer \\ USB Host | | USB = USB-UART \\ USB-JTAG Programmer \\ USB Host | ||
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===== Documentation ===== | ===== Documentation ===== | ||
{{topic> | {{topic> | ||
+ | |||
+ | **Note:** //Xilinx software tools are not available for download in some countries. Prior to purchasing the Cora Z7, please check the supporting software' | ||
+ | |||
---- | ---- | ||
===== Tutorials ===== | ===== Tutorials ===== | ||
+ | |||
* [[programmable-logic: | * [[programmable-logic: | ||
* Walks through installing Vivado and Vitis, the development environments used to create hardware and software applications targeting Digilent FPGA development boards. | * Walks through installing Vivado and Vitis, the development environments used to create hardware and software applications targeting Digilent FPGA development boards. | ||
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* [[programmable-logic: | * [[programmable-logic: | ||
* Walks through using Vivado to create a simple design that blinks a single LED. | * Walks through using Vivado to create a simple design that blinks a single LED. | ||
- | + | | |
- | --> Legacy Xilinx Tools Tutorials # | + | * Digilent Pmod IPs can be used to control connected Pmods from baremetal software. |
- | + | * It should be noted that not all Pmods are supported and that Pmod IPs are only supported in versions of Vivado 2019.1 and older. | |
- | The following guides support Vivado and Xilinx SDK. Check the individual guides for information on which versions of these tools they support. | + | * [[programmable-logic/guides/zynq-baremetal-boot]] |
- | + | * [[programmable-logic:guides:zynq-servers]] | |
- | | + | |
- | * [[vivado/ | + | |
- | * [[vivado/getting_started/2018.2]] | + | |
- | * [[programmable-logic/guides/installing-vivado-and-sdk]] | + | |
- | + | ||
- | <-- | + | |
---- | ---- | ||
===== Example Projects ===== | ===== Example Projects ===== | ||
- | === Demos Supporting Vivado and Vitis 2020.1 === | + | === Demos Supporting Vivado and Vitis 2022.1 === |
* [[./ | * [[./ | ||
* [[./ | * [[./ | ||
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===== Additional Resources ===== | ===== Additional Resources ===== | ||
+ | * {{https:// | ||
{{topic> | {{topic> | ||
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---- | ---- | ||
- | {{tag> | + | {{tag> |