Cmod A7 XADC Demo

This simple XADC demo is a verilog project made to demonstrate the ADC functionality of the Cmod-A7

• The RGB LED brightens the RED LED when the read voltage goes up.
• When BTN1 is pressed, the demo switches which xadc pin to read from.

This demo uses XADC ports 4 and 12 since they are the channels connected to pin 15 and 16. This can be seen in the schematic below.

• Basic familiarity with Vivado
  • This experience can be found by walking through our “Getting Started with Vivado” guide

• Cmod A7 FPGA board
• Micro-USB cable
• Breadboard
• Resistors
• Wire

• Vivado Design Suite 2015.X
  • Newer/older versions can be used, but the procedure may vary slightly

Cmod A7 Support Repository – GIT Repo

1.1) Download the repository linked in the download section and place it in the location of your choosing.

1.2) Generate the XADC project in the Projects folder by following this guide before continuing: How to Generate a Project from Digilent's Github

2.1) Click Generate Bitstream on the left hand menu towards the bottom. Vivado will run through both Run Synthesis and Run Implementation before it generates the bitstream automatically.

Note: If you want, you can click each step by itself in the order of Run Synthesis, Run Implementation and then Generate Bitstream.

3.1) Once you have generated your bit file, Click on the hardware manager and connect to your board by choosing the local server option.

3.2) Click program to load the project onto your Cmod A7.

This portion will help you run the demo and observe all its features.