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Files in learn:courses:digital-projects:hierarchial-design-in-verilog
- counter.zip
- 2023/10/20 17:39
- 300 B
- demultiplexor.png
- 340×160
- 2023/10/20 17:33
- 4 KB
- demux.png
- 232×113
- 2023/10/20 17:34
- 2.4 KB
- latch.zip
- 2023/10/20 17:39
- 244 B
- transsys.png
- 564×237
- 2023/10/20 17:40
- 13.8 KB
- wrapper.png
- 361×220
- 2023/10/20 17:36
- 8 KB
![[root]](https://digilent.com/reference/learn/courses/unit-6/start?ns=&tab_files=files&do=media&tab_details=view&image=learn%3Acourses%3Adigital-projects%3Ahierarchial-design-in-verilog%3Atranssys.png){kind=link}
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- Date:
- 2023/10/20 17:40
- Filename:
- transsys.png
- Format:
- PNG
- Size:
- 14KB
- Width:
- 564
- Height:
- 237
- References for:
- Project 5: A Simple Communications System