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anvyl:refmanual [2014/09/11 21:12] – Joshua Woldstad | anvyl:refmanual [2016/04/11 16:33] (current) – Martha | ||
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* GPIO: 14 LEDs (10 red, 2 yellow, 2 green), 8 slide switches, 8 DIP switches in 2 groups and 4 push buttons | * GPIO: 14 LEDs (10 red, 2 yellow, 2 green), 8 slide switches, 8 DIP switches in 2 groups and 4 push buttons | ||
* breadboard with 10 Digital I/ | * breadboard with 10 Digital I/ | ||
- | * 32 I/O’s routed to 40-pin expansion connector (I/O’s are shared with Pmod connectors) | + | * 32 I/O’s routed to 40-pin expansion connector (I/O’s are shared with Pmod ports) |
- | * seven 12-pin Pmod connectors | + | * seven 12-pin Pmod ports with 56 I/O’s total |
* ships with a 20W power supply and USB cable | * ships with a 20W power supply and USB cable | ||
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====== Flash Memory ====== | ====== Flash Memory ====== | ||
- | {{ : | + | {{ : |
The Anvyl board uses a 128Mbit Numonyx N25Q128 Serial flash memory device (organized as 16Mbit by 8) for non-volatile storage of FPGA configuration files. The SPI Flash can be programmed with a .mcs file using the iMPACT software. An FPGA configuration file requires less than 12Mbits, leaving 116Mbits available for user data. Data can be transferred to and from a PC to/from the flash device by user applications, | The Anvyl board uses a 128Mbit Numonyx N25Q128 Serial flash memory device (organized as 16Mbit by 8) for non-volatile storage of FPGA configuration files. The SPI Flash can be programmed with a .mcs file using the iMPACT software. An FPGA configuration file requires less than 12Mbits, leaving 116Mbits available for user data. Data can be transferred to and from a PC to/from the flash device by user applications, | ||
A board test/ | A board test/ | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== Ethernet PHY ====== | ||
+ | |||
+ | The Anvyl board includes an SMSC 10/100 mbps PHY (LAN8720A-CP-TR) paired with a Halo HFJ11-2450E RJ-45 connector. The PHY is connected to the FPGA using a RMII configuration. It is configured to boot into “All Capable, with Auto Negotiation Enabled” mode on power-on. The data sheet for the SMSC PHY is available from the SMSC website. | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== HDMI Output ====== | ||
+ | |||
+ | The Anvyl board contains one unbuffered HDMI output port. The unbuffered port uses an HDMI type A connector. Since the HDMI and DVI systems use the same TMDS signaling standard, a simple adaptor (available at most electronics stores) can be used to drive a DVI connector from the HDMI output port. The HDMI connector does not include VGA signals, so analog displays cannot be driven. | ||
+ | |||
+ | The 19-pin HDMI connectors include four differential data channels, five GND connections, | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== VGA ====== | ||
+ | |||
+ | The Anvyl provides a 12bit VGA interface which allows up to 4096 colors displayed on a standard VGA Monitor. The five standard VGA signals Red, Green, Blue, Horizontal Sync (HS), and Vertical Sync (VS) are routed directly from the FPGA to the VGA connector. There are four signals routed from the FPGA for each of the standard VGA color signals resulting in a video system that can produce 4,096 colors. Each of these signals has a series resistor that when combined in the circuit, form a divider with the 75-ohm termination resistance of the VGA display. These simple circuits ensure that the video signals cannot exceed the VGA-specified maximum voltage, and result in color signals that are either fully on (.7V), fully off (0V) or somewhere in between. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | //Fig. 2. VGA interface.// | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | // Fig. 3. HD DB-15 connector, PCB hole pattern, pin assignments, | ||
+ | |||
+ | CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs). Color CRT displays use three electron beams (one for red, one for blue, and one for green) to energize the phosphor that coats the inner side of the display end of a cathode ray tube (see Fig. 1). Electron beams emanate from “electron guns”, which are finely-pointed heated cathodes placed in close proximity to a positively charged annular plate called a “grid”. The electrostatic force imposed by the grid pulls rays of energized electrons from the cathodes, and those rays are fed by the current that flows into the cathodes. These particle rays are initially accelerated towards the grid, but they soon fall under the influence of the much larger electrostatic force that results from the entire phosphor-coated display surface of the CRT being charged to 20kV (or more). The rays are focused to a fine beam as they pass through the center of the grids, and then they accelerate to impact on the phosphor-coated display surface. The phosphor surface glows brightly at the impact point, and it continues to glow for several hundred microseconds after the beam is removed. The larger the current fed into the cathode, the brighter the phosphor will glow. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | //Fig. 4. Cathode ray tube display system.// | ||
+ | |||
+ | Between the grid and the display surface, the electron beam passes through the neck of the CRT where two coils of wire produce orthogonal electromagnetic fields. Because cathode rays are composed of charged particles (electrons), | ||
+ | |||
+ | ==== VGA System Timing ==== | ||
+ | |||
+ | VGA signal timings are specified, published, copyrighted and sold by the VESA organization (www.vesa.org). The following VGA system timing information is provided as an example of how a VGA monitor might be driven with a resolution of 640x480. For more precise information, | ||
+ | |||
+ | Information is only displayed when the beam is moving “forward” (left to right and top to bottom), and not during the time the beam is reset back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass. The size of the beams, the frequency at which the beam can be traced across the display, and the frequency at which the electron beam can be modulated determine the display resolution. Modern VGA displays can accommodate different resolutions, | ||
+ | |||
+ | Video data typically comes from a video refresh memory, with one or more bytes assigned to each pixel location (the Anvyl uses four bits per pixel). The controller must index into video memory as the beams move across the display, and retrieve and apply video data to the display at precisely the time the electron beam is moving across a given pixel. | ||
+ | |||
+ | |||
+ | {{ : | ||
+ | //Fig. 5. VGA horizontal synchronization.// | ||
+ | |||
+ | A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video data based on the pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be displayed at a given refresh frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in the table below can be derived. Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync pulse times during which information cannot be displayed) are based on observations taken from actual VGA displays. | ||
+ | |||
+ | A VGA controller circuit decodes the output of a horizontal-sync counter driven by the pixel clock to generate HS signal timings. This counter can be used to locate any pixel location on a given row. | ||
+ | |||
+ | Likewise, the output of a vertical-sync counter that increments with each HS pulse can be used to generate VS signal timings, and this counter can be used to locate any given row. These two continually running counters can be used to form an address into video RAM. No time relationship between the onset of the HS pulse and the onset of the VS pulse is specified, so the designer can arrange the counters to easily form video RAM addresses, or to minimize decoding logic for sync pulse generation. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | //Fig. 6. VGA sync signal timings.// | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | //Fig. 7. VGA display controller block diagram.// | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== Audio (I2S) ====== | ||
+ | |||
+ | The Anvyl board includes an Analog Devices audio codec SSM2603CPZ (IC5) with four 1/8” audio jacks for line-out (J7), headphone-out (J6), line-in (J9), and microphone-in (J8). | ||
+ | Audio data sampling at up to 24 bits and 96KHz is supported, and the audio in (record) and audio out (playback) sampling rates can be set independently. The microphone jack is mono, and all other jacks are stereo. The headphone jack is driven by the audio codec' | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== Touchscreen TFT Display ====== | ||
+ | |||
+ | A 4.3” wide-format vivid color LED backlit LCD screen is used on the Anvyl. The screen has a 480×272 native resolution display with a color depth of 24 bits per pixel. A four-wire resistive touchscreen with antiglare coating covers the entire active display area. The LCD screen and the touchscreen can be used independently. Touch readings are noisier when the LCD is on, but you can filter the noise and still obtain a fast sample rate. If you require maximum precision and sample rates, you should turn the LCD off during touchscreen sampling. | ||
+ | |||
+ | To display an image, the LCD needs to be continuously driven with properly-timed data. This data consists of the lines and blanking periods that form video frames. Each frame consists of 272 active lines and several vertical blanking lines. Each line consists of 480 active pixel periods and several horizontal blanking periods. | ||
+ | |||
+ | For additional information on using the TFT Display, refer to the Vmod-TFT reference manual. The Anvyl and the Vmod-TFT use the same display hardware and require the same control signals. Reference designs that use the Anvyl touchscreen TFT display can be found on the Anvyl product page. | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== OLED ====== | ||
+ | |||
+ | An Inteltronic/ | ||
+ | |||
+ | The Anvyl contains the same OLED circuit as the PmodOLED, with the exception that CS# is pulled low, enabling the display by default. For additional information on driving the Anvyl OLED, refer to the PmodOLED reference manual. Reference designs that use the Anvyl OLED display can be found on the Anvyl product page. | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== USB-UART Bridge (Serial Port) ====== | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | The Anvyl includes an FTDI FT2232HQ USB-UART bridge to allow PC applications to communicate with the board using standard Windows COM port commands. Free USB-COM port drivers, available from www.ftdichip.com under the " | ||
+ | |||
+ | The FT2232HQ, attached to port J12, is also used as the controller for the Digilent USB-JTAG circuitry, but these two functions behave entirely independent of one another. Programmers interested in using the UART functionality of the FT2232 within their design do not need to worry about the JTAG circuitry interfering with their data, and vice-versa. | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== USB HID Hosts ====== | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | Two Microchip PIC24FJ128GB106 microcontrollers provide the Anvyl with USB HID host capability. Firmware in the microcontrollers can drive a mouse or a keyboard attached to the type A USB connectors at J13 and J14 labeled " | ||
+ | |||
+ | The “HOST” PIC24 drives four signals into the FPGA – two are dedicated as a keyboard/ | ||
+ | |||
+ | ==== HID Controller ==== | ||
+ | |||
+ | To access a USB host controller, EDK designs can use the standard PS/2 core (non-EDK designs can use a simple state machine). | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | Mice and keyboards that use the PS/2 protocol¹ | ||
+ | |||
+ | ¹Not all keyboard manufacturers strictly adhere to the PS/2 specifications; | ||
+ | |||
+ | ==== Keyboard ==== | ||
+ | |||
+ | The keyboard uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports). | ||
+ | |||
+ | PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms. When a key is released, an F0 (binary “11110000”) key-up code is sent, followed by the scan code of the released key. If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an E0 (binary “11100000”) ahead of the scan code (and they may send more than one scan code). When an extended key is released, an E0 F0 key-up code is sent, followed by the scan code. Scan codes for most keys are shown in the figure. A host device can also send data to the keyboard. Below is a short list of some common commands a host might send. | ||
+ | |||
+ | | ED | Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns FA after receiving ED, then host sends a byte to set LED status: bit 0 sets Scroll Lock, bit 1 sets Num Lock, and bit 2 sets Caps lock. Bits 3 to 7 are ignored. | ||
+ | | EE | Echo (test). Keyboard returns EE after receiving EE. | | ||
+ | | F3 | Set scan code repeat rate. Keyboard returns F3 on receiving FA, then host sends second byte to set the repeat rate. | | ||
+ | | FE | Resend. FE directs keyboard to re-send most recent scan code. | | ||
+ | | FF | Reset. Resets the keyboard | ||
+ | |||
+ | The keyboard can send data to the host only when both the data and clock lines are high (or idle). Since the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host pulls the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30KHz) when the data is sent, and data is valid on the falling edge of the clock. | ||
+ | |||
+ | Scan codes for most PS/2 keys are shown in the figure below. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | //Fig. 11. PS/2 keyboard scan codes. | ||
+ | // | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== Mouse ====== | ||
+ | |||
+ | The mouse outputs a clock and data signal when it is moved, otherwise, these signals remain at logic ‘1’. Each time the mouse is moved, three 11-bit words are sent from the mouse to the host device. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 bits of data (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Thus, each data transmission contains 33 bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 11, 21, and 33 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in the figure above. Data is valid at the falling edge of the clock, and the clock period is 20 to 30KHz. | ||
+ | |||
+ | The mouse assumes a relative coordinate system wherein moving the mouse to the right generates a positive number in the X field, and moving to the left generates a negative number. Likewise, moving the mouse up generates a positive number in the Y field, and moving down represents a negative number (the XS and YS bits in the status byte are the sign bits – a ‘1’ indicates a negative number). The magnitude of the X and Y numbers represent the rate of mouse movement – the larger the number, the faster the mouse is moving (the XV and YV bits in the status byte are movement overflow indicators – a ‘1’ means overflow has occurred). If the mouse moves continuously, | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | //Fig. 12. Mouse navigation bytes.// | ||
+ | |||
+ | ====== Keypad ====== | ||
+ | |||
+ | The Anvyl keypad has 16 labeled keys (0-F). It is set up as a matrix in which each row of buttons from left to right are tied to a row pin, and each column from top to bottom | ||
+ | is tied to a column pin. This gives the user four row pins and four column pins to address a button push. When a button is pressed, the pins corresponding to that button’s row and column are connected. | ||
+ | |||
+ | To read a button’s state, the column pin in which the button resides must be driven low while the other three column pins are driven high. This enables all of the buttons in that column. When a button in that column is pushed, the corresponding row pin will read logic low. | ||
+ | |||
+ | The state of all 16 buttons can be determined in a four-step process by enabling each of the four columns one at a time. This can be accomplished by rotating an “1110” pattern through the column pins. During each step, the logic levels of the row pins correspond to the state of the buttons in that column. | ||
+ | |||
+ | To allow simultaneous button presses in the same row, instead configure the column pins as bi-directional with internal pull-up resistors and keep the columns not currently being read at high impedance. | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | ^ Keypad Pinout | ||
+ | | ROW1: | E4 | | ||
+ | | ROW2: | F3 | | ||
+ | | ROW3: | G8 | | ||
+ | | ROW4: | G7 | | ||
+ | | COL1: | H8 | | ||
+ | | COL2: | J7 | | ||
+ | | COL3: | K8 | | ||
+ | | COL4: | K7 | | ||
+ | |||
+ | |||
+ | //Fig. 13. Keypad schematic | ||
+ | // | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== Oscillators/ | ||
+ | |||
+ | The Anvyl board includes a single 100MHz Crystal oscillator connected to pin D11 (D11 is a GCLK input in bank 0). The input clock can drive any or all of the four clock management tiles in the Spartan-6. Each tile includes two Digital Clock Managers (DCMs) and one Phase-Locked Loop (PLLs).DCMs provide the four phases of the input frequency (0º, 90º, 180º, and 270º), a divided clock that can be the input clock divided by any integer from 2 to 16 or 1.5, 2.5, 3.5... 7.5, and two antiphase clock outputs that can be multiplied by any integer from 2 to 32 and simultaneously divided by any integer from 1 to 32. | ||
+ | |||
+ | PLLs use Voltage Controlled Oscillators (VCOs) that can be programmed to generate frequencies in the 400MHz to 1080MHz range by setting three sets of programmable dividers during FPGA configuration. VCO outputs have eight equally-spaced outputs (0º, 45º, 90º, 135º, 180º, 225º, 270º, and 315º) that can be divided by any integer between 1 and 128. | ||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== Basic I/O ====== | ||
+ | |||
+ | The Anvyl board includes fourteen LEDs (ten red, two yellow, and two green), eight slide switches, eight DIP switches in two groups, four push buttons, three two-digit seven-segment displays, and a 630 tie-point breadboard with ten digital I/O’s. The push buttons, slide switches and DIP switches are connected to the FPGA via series resistors to prevent damage from inadvertent short circuits (a short circuit could occur if an FPGA pin assigned to a pushbutton or slide switch was inadvertently defined as an output). The pushbuttons are " | ||
+ | |||
+ | | //**Push Buttons**// | ||
+ | | BTN0: | E6 | SW0: | V5 | DIP8-1: | ||
+ | | BTN1: | D5 | SW1: | U4 | DIP8-2: | ||
+ | | BTN2: | A3 | SW2: | V3 | DIP8-3: | ||
+ | | BTN3: | AB9 | SW3: | P4 | DIP8-4: | ||
+ | | | | SW4: | R4 | DIP9-1: | ||
+ | | | | SW5: | P6 | DIP9-2: | ||
+ | | | | SW6: | P5 | DIP9-3: | ||
+ | | | | SW7: | P8 | DIP9-4: | ||
+ | | | | | | ||
+ | | | | | | ||
+ | | | | | | ||
+ | | | | | | ||
+ | | | | | | ||
+ | | | | | | ||
+ | |||
+ | |||
+ | ---- | ||
+ | |||
+ | ====== Seven Segment Displays ====== | ||
+ | |||
+ | The Anvyl board contains three 2-digit common cathode seven-segment LED displays. Each of the two digits is composed of seven segments arranged in a “figure eight” pattern, with an LED embedded in each segment. Segment LEDs can be individually illuminated, | ||
+ | |||
+ | The common cathode signals are available as six “digit enable” input signals to the three 2-digit displays. The anodes of similar segments on all six digits are connected into seven circuit nodes labeled AA through AG (so, for example, the six “D” anodes from the six digits are grouped together into a single circuit node called “AD”). These seven anode signals are available as inputs to the 2-digit displays. This signal connection scheme creates a multiplexed display, where the anode signals are common to all digits but they can only illuminate the segments of the digit whose corresponding cathode signal is asserted. | ||
+ | |||
+ | A scanning display controller circuit can be used to show a two-digit number on each display. This circuit drives the cathode signals and corresponding anode patterns of each digit in a repeating, continuous succession, at an update rate that is faster than the human eye response. Each digit is illuminated just one-sixth of the time, but because the eye cannot perceive the darkening of a digit before it is illuminated again, the digit appears continuously illuminated. If the update (or “refresh”) rate is slowed to a given point (around 45 hertz), then most people will begin to see the display flicker. | ||
+ | |||
+ | In order for each of the six digits to appear bright and continuously illuminated, | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | //Fig. 14. Seven-segment displays.// | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | ====== Expansion Connectors ====== | ||
+ | |||
+ | The Anvyl board has a 2x20 pin connector and seven 12-pin Pmod ports. Pmod ports are 2x6 right-angle, | ||
+ | |||
+ | {{ : | ||
+ | |||
+ | The 40-pin expansion connector has 32 I/O signals that are shared with Pmods JD, JE, JF and JG. It also provides GND, VCC3V3, and VCC5V0 connections. | ||
+ | |||
+ | | //**Pmod JA**// | ||
+ | | JA1: | AA18 | JB1: | Y16 | JC1: | Y10 | JD1: | AB13 | JE1: | U10 | JF1: | V7 | JG1: | V20 | | ||
+ | | JA2: | AA16 | JB2: | AB14 | JC2: | AB12 | JD2: | Y12 | JE2: | V9 | JF2: | W6 | JG2: | T18 | | ||
+ | | JA3: | Y15 | JB3: | Y14 | JC3: | AB11 | JD3: | T11 | JE3: | Y8 | JF3: | Y7 | JG3: | D17 | | ||
+ | | JA4: | V15 | JB4: | U14 | JC4: | AB10 | JD4: | W10 | JE4: | AA8 | JF4: | AA6 | JG4: | B18 | | ||
+ | | JA7: | AB18 | JB7: | AA14 | JC7: | AA12 | JD7: | W12 | JE7: | U9 | JF7: | W8 | JG7: | T17 | | ||
+ | | JA8: | AB16 | JB8: | W14 | JC8: | Y11 | JD8: | R11 | JE8: | W9 | JF8: | Y6 | JG8: | A17 | | ||
+ | | JA9: | AB15 | JB9: | T14 | JC9: | AA10 | JD9: | V11 | JE9: | Y9 | JF9: | AB7 | JG9: | C16 | | ||
+ | | JA10: | W15 | JB10: | W11 | JC10: | Y13 | JD10: | T10 | JE10: | AB8 | JF10: | AB6 | JG10: | A18 | | ||
+ | |||
+ | //Table 2. Pmod pinout.// | ||
+ | |||
+ | |||