Differences
This shows you the differences between two versions of the page.
Both sides previous revisionPrevious revisionNext revision | Previous revisionLast revisionBoth sides next revision | ||
sume:refmanual [2015/03/10 04:10] – [NetFPGA Organization] sbobrowicz | sume:refmanual [2016/04/11 16:43] – Martha | ||
---|---|---|---|
Line 7: | Line 7: | ||
32 GTH serial transceivers have been used to provide access to 8 lanes of end-point PCI-E (Gen3 x8), | 32 GTH serial transceivers have been used to provide access to 8 lanes of end-point PCI-E (Gen3 x8), | ||
- | 4 SFP+ (10Gbps) ports, 2 SATA-III ports (6Gbps) and 18 data-rate-adjustable GTH ports through a HPC-FMC connector | + | 4 SFP+ (10Gbps) ports, 2 SATA-III ports (6Gbps), and 18 data-rate-adjustable GTH ports through a HPC-FMC connector |
and a QTH connector. | and a QTH connector. | ||
- | Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications. | + | Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications. |
- | The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[http:// | + | The NetFPGA SUME is compatible with Xilinx’s new high-performance Vivado® Design Suite as well as the ISE® toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA SUME. Licensing information for Vivado can be found [[http:// |
A simplified block diagram that depicts the major features of the NetFPGA SUME is seen in figure 1. | A simplified block diagram that depicts the major features of the NetFPGA SUME is seen in figure 1. | ||
Line 37: | Line 37: | ||
* Four globally unique MAC addresses | * Four globally unique MAC addresses | ||
* USB-UART | * USB-UART | ||
- | * I2C Pmod Connector | + | * I2C Pmod Port |
* Expansion Connectors | * Expansion Connectors | ||
* QTH Connector (8 GTH transceivers) | * QTH Connector (8 GTH transceivers) | ||
* One HPC FMC Connector (10 GTH transceivers and 68 User I/Os) | * One HPC FMC Connector (10 GTH transceivers and 68 User I/Os) | ||
- | * One 12-pin Pmod Connector | + | * One 12-pin Pmod Port (8 User I/Os) |
* Programming | * Programming | ||
* Micro USB Connector for JTAG programming and debugging (shared with USB-UART interface) | * Micro USB Connector for JTAG programming and debugging (shared with USB-UART interface) | ||
Line 59: | Line 59: | ||
This board is supported by reference designs and IP created by the NetFPGA organization. | This board is supported by reference designs and IP created by the NetFPGA organization. | ||
- | For more information on the NetFPGA organization, | + | For more information on the NetFPGA organization, |
===== Functional Description ===== | ===== Functional Description ===== | ||
Line 66: | Line 66: | ||
=== Input Supply === | === Input Supply === | ||
- | The NetFPGA-SUME receives power via a 2 x 4 pin PCI Express Auxiliary Power Connector. The 2 x 4 pin PCI Express Auxiliary Power receptacle (header J14) can accept both 2 x 3 and 2 x 4 pin PCI Express Auxiliary Power Plugs found on a standard ATX power supply. When installed on a PC motherboard, | + | The NetFPGA-SUME receives power via a 2x4 pin PCI Express Auxiliary Power Connector. The 2x4 pin PCI Express Auxiliary Power receptacle (header J14) can accept both 2x3 and 2x4 pin PCI Express Auxiliary Power Plugs found on a standard ATX power supply. When installed on a PC motherboard, |
{{ : | {{ : | ||
//Figure 2. Pin 15 and 16 of Standard ATX power supply shorted together.// | //Figure 2. Pin 15 and 16 of Standard ATX power supply shorted together.// | ||
- | According to Revision 1.0 of the //PCI Express 225 W/300 W High Power Card Electromechanical Specification// | + | According to Revision 1.0 of the //PCI Express 225 W/300 W High Power Card Electromechanical Specification// |
{{ : | {{ : | ||
//Figure 3. Power Connector (J14).// | //Figure 3. Power Connector (J14).// | ||
- | Figure 3 describes pin-out of the power connector (header J14) when a 2 x 4 pin or a 2 x 3 pin plug is used. The Sense0 and Sense1 pins are to be connected to GND when power is present, and left floating otherwise. Since the 2 x 3 pin plug does not include a Sense1 pin it’s possible to determine what type of plug is present, and thus how much power can be consumed. | + | Figure 3 describes pin-out of the power connector (header J14) when a 2x4 pin or a 2x3 pin plug is used. The Sense0 and Sense1 pins are to be connected to GND when power is present, and left floating otherwise. Since the 2x3 pin plug does not include a Sense1 pin, it's possible to determine what type of plug is present, and thus how much power can be consumed. |
- | The FPGA logic can determine whether or not a 2 x 4 pin is present by enabling an internal pull-up on pin AW42 and then checking the state of that pin. If logic ‘0’ is seen on AW42 then a 2 x 4 plug is connected and up to 150 watts of power can be drawn. If logic ‘1’ is son on AW42 then a 2 x3 plug is connected, and the board’s power consumption should be limited to 75 watts or less. | + | The FPGA logic can determine whether or not a 2x4 pin is present by enabling an internal pull-up on pin AW42 and then checking the state of that pin. If logic '0' |
=== Power Supply Topology === | === Power Supply Topology === | ||
- | The high performance Virtex 7 FPGA, QDRII+ memories, and DDR3 memories featured on the NetFPGA-SUME require several different supply voltages (supply rails) in order to function. These components also require that the supply rails are sequenced on and off in a particular order. Table 1 lists the various supply rails, their nominal voltages, and rated output currents. | + | The high performance Virtex-7 FPGA, QDRII+ memories, and DDR3 memories featured on the NetFPGA-SUME require several different supply voltages (supply rails) in order to function. These components also require that the supply rails are sequenced on and off in a particular order. Table 1 lists the various supply rails, their nominal voltages, and rated output currents. |
^ Supply Rail ^ Nominal Voltage | ^ Supply Rail ^ Nominal Voltage | ||
Line 97: | Line 97: | ||
//Table 1. Supply rails, voltages, and currents.// | //Table 1. Supply rails, voltages, and currents.// | ||
- | These supply rails are derived from the 12V input (VCC12V0, comes from header J14) using eight high efficiency switching regulators and one low drop out (LDO) linear regulator from Linear Technology. Since both the DDR3 and QDRII+ I/O supplies are powered from the VCC1V5 rail two ferrite beads are also included to prevent high speed switching noise caused by one memory from affecting the other. Figure 5 shows how the various supplies are derived from the input. | + | These supply rails are derived from the 12V input (VCC12V0, comes from header J14) using eight high efficiency switching regulators and one low drop out (LDO) linear regulator from Linear Technology. Since both the DDR3 and QDRII+ I/O supplies are powered from the VCC1V5 rail, two ferrite beads are also included to prevent high speed switching noise caused by one memory from affecting the other. Figure 5 shows how the various supplies are derived from the input. |
- | A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks. Each clock is 60 degrees out of phase with any of the other clock outputs (see Fig. 4). These out of phase clocks are used as the input clocks for the regulators that produce the high power output supply rails (VCC1V0, VCC1V5, VCC1V8, VCC3V3, and MGTAVCC). The LTC3839, which produces the VCC1V0 supply rail, is a dual phase convertor | + | A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks. Each clock is 60 degrees out of phase with any of the other clock outputs (see Fig. 4). These out of phase clocks are used as the input clocks for the regulators that produce the high power output supply rails (VCC1V0, VCC1V5, VCC1V8, VCC3V3, and MGTAVCC). The LTC3839, which produces the VCC1V0 supply rail, is a dual phase converter |
{{ : | {{ : | ||
Line 109: | Line 109: | ||
=== Power Supply Sequencing and Supervising === | === Power Supply Sequencing and Supervising === | ||
- | The components on the NetFPGA-SUME require that the supply voltages be sequenced on and off in a particular order. The NetFPGA-SUME utilizes two Linear Technology | + | The components on the NetFPGA-SUME require that the supply voltages be sequenced on and off in a particular order. The NetFPGA-SUME utilizes two Linear Technology |
{{ : | {{ : | ||
//Figure 6. LTC2974 Sequencer and Supervisor.// | //Figure 6. LTC2974 Sequencer and Supervisor.// | ||
- | Figure 6 depicts the connections between the two LTC2974’s, as well as the signals that are used to control the power on and off sequence. When the input voltage (VCC12V0) exceeds 10 volts the LTC2974’s | + | Figure 6 depicts the connections between the two LTC2974s, as well as the signals that are used to control the power on and off sequence. When the input voltage (VCC12V0) exceeds 10 volts, the LTC2974s |
- VCC1V0 | - VCC1V0 | ||
- VCC1V8 | - VCC1V8 | ||
Line 124: | Line 124: | ||
- MGTVAUX | - MGTVAUX | ||
- | When the input voltage falls below 9 volts, or the power switch transitions to the “OFF” position, the LTC2974’s | + | When the input voltage falls below 9 volts, or the power switch transitions to the "OFF" |
- MGTVAUX | - MGTVAUX | ||
- VCC1V5, QDRVTT, and DDRVTT | - VCC1V5, QDRVTT, and DDRVTT | ||
Line 135: | Line 135: | ||
{{ : | {{ : | ||
- | //Figure 7.Power ON/OFF Sequence.// | + | //Figure 7. Power ON/OFF Sequence.// |
- | The LTC2974’s | + | The LTC2974s |
- | In order to generate faults and warnings each channel of the LTC2974 must be configured with a nominal output voltage, under voltage warning limit, over voltage fault limit, under current warning limit, over current warning limit, over current fault limit, under current fault limit, under temperature warning limit, under temperature fault limit, and over temperature fault limit. Tables 2 and 3 describe the voltage and current limits as pre-configured | + | In order to generate faults and warnings, each channel of the LTC2974 must be configured with a nominal output voltage, under voltage warning limit, over voltage fault limit, under current warning limit, over current warning limit, over current fault limit, under current fault limit, under temperature warning limit, under temperature fault limit, and over temperature fault limit. Tables 2 & 3 describe the voltage and current limits as preconfigured |
^ Supply Rail ^ Under Voltage Fault Limit ^ Under Voltage Warning Limit ^ Nominal Voltage | ^ Supply Rail ^ Under Voltage Fault Limit ^ Under Voltage Warning Limit ^ Nominal Voltage | ||
Line 154: | Line 154: | ||
//Table 2. Voltage fault and warning limits.// | //Table 2. Voltage fault and warning limits.// | ||
- | //Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974’s.// | + | //Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974s.// |
^ Supply Rail ^ Undercurrent Fault Limit ^ Rated Current | ^ Supply Rail ^ Undercurrent Fault Limit ^ Rated Current | ||
Line 170: | Line 170: | ||
//Table 3. Current fault and warning limits.// | //Table 3. Current fault and warning limits.// | ||
- | //Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974’s.// | + | //Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974s.// |
=== Fault and Warning Interrupt Sources === | === Fault and Warning Interrupt Sources === | ||
Line 176: | Line 176: | ||
When the LTC2974 detects a fault or a warning condition it may signal an interrupt by driving the ALERTB, AUXFAULTB, or FAULTB1 pins. | When the LTC2974 detects a fault or a warning condition it may signal an interrupt by driving the ALERTB, AUXFAULTB, or FAULTB1 pins. | ||
- | The ALERTB pin of the LTC2974 is an open drain output that is driven low whenever a fault or warning occurs. The ALERTB pins of the two LTC2974’s | + | The ALERTB pin of the LTC2974 is an open drain output that is driven low whenever a fault or warning occurs. The ALERTB pins of the two LTC2974s |
* Output overvoltage or under voltage fault/ | * Output overvoltage or under voltage fault/ | ||
* Output over current or under current fault/ | * Output over current or under current fault/ | ||
Line 182: | Line 182: | ||
* Channel output voltage has not reached or exceeded the under voltage fault limit set for that channel within TON_MAX_FAULT_LIMIT milliseconds (set to 15ms) of the output being enabled | * Channel output voltage has not reached or exceeded the under voltage fault limit set for that channel within TON_MAX_FAULT_LIMIT milliseconds (set to 15ms) of the output being enabled | ||
- | When any of the above faults occur the PCON_ALERT_B net will be driven low until the fault condition has been removed and the CLEAR_FAULTS command has been sent to both of the LTC2974’s | + | When any of the above faults occur the PCON_ALERT_B net will be driven low until the fault condition has been removed and the CLEAR_FAULTS command has been sent to both of the LTC2974s |
{{ : | {{ : | ||
//Figure 8. ALERTB Interrupt Source.// | //Figure 8. ALERTB Interrupt Source.// | ||
- | The AUXFAULTB pins of the two LTC2974’s | + | The AUXFAULTB pins of the two LTC2974s |
* Output overvoltage fault on any channel | * Output overvoltage fault on any channel | ||
* Output over current or under current fault on any channel | * Output over current or under current fault on any channel | ||
Line 194: | Line 194: | ||
{{ : | {{ : | ||
- | //Figure 9. AUXFAULTB | + | //Figure 9. AUXFAULTB |
- | The FAULTB1 pin of the LTC2974 is bi-directional open-drain input/ | + | The FAULTB1 pin of the LTC2974 is bi-directional open-drain input/ |
- | The FAULTB1 pin of the two LTC2974’s | + | The FAULTB1 pin of the two LTC2974s |
{{ : | {{ : | ||
- | //Figure 10. FAULTB1 | + | //Figure 10. FAULTB1 |
=== Power Consumption === | === Power Consumption === | ||
Line 233: | Line 233: | ||
%% | %% | ||
- | Determining the input power consumption after taking into account the 10 Watt output power limitation of the FMC connector is difficult, as we do not know which supply rails will be utilized by an attached FMC mezzanine module. Assuming that all power was consumed from VADJ and 3P3V the total input power consumption would be reduced by | + | Determining the input power consumption after taking into account the 10 Watt output power limitation of the FMC connector is difficult, as we do not know which supply rails will be utilized by an attached FMC mezzanine module. Assuming that all power was consumed from VADJ and 3P3V, the total input power consumption would be reduced by |
12+((19.1-12)/ | 12+((19.1-12)/ | ||
(40+22.5+(1.8*11)+(3.3*12)+8+3.6)/ | (40+22.5+(1.8*11)+(3.3*12)+8+3.6)/ | ||
Line 240: | Line 240: | ||
After power-on, the Virtex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of two ways: | After power-on, the Virtex-7 FPGA must be configured (or programmed) before it can perform any functions. You can configure the FPGA in one of two ways: | ||
- | - A PC can use the Digilent USB-JTAG circuitry (port J16, labeled | + | - A PC can use the Digilent USB-JTAG circuitry (port J16, labeled |
- One of four bitstream files stored in the parallel flash can be loaded by the onboard CPLD. | - One of four bitstream files stored in the parallel flash can be loaded by the onboard CPLD. | ||
{{ : | {{ : | ||
- | The figure above shows the different options available for configuring the FPGA. An on-board | + | The figure above shows the different options available for configuring the FPGA. An on-board |
The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs). | The FPGA configuration data is stored in files called bitstreams that have the .bit file extension. The ISE or Vivado software from Xilinx can create bitstreams from VHDL, Verilog®, or schematic-based source files (in the ISE toolset, EDK is used for MicroBlaze™ embedded processor-based designs). | ||
Line 253: | Line 253: | ||
A Virtex-7 690T bitstream is typically 229,878,496 bits and can take a long time to transfer. The time it takes to program the NetFPGA-SUME can be decreased by compressing the bitstream before programming, | A Virtex-7 690T bitstream is typically 229,878,496 bits and can take a long time to transfer. The time it takes to program the NetFPGA-SUME can be decreased by compressing the bitstream before programming, | ||
- | After being successfully programmed, the FPGA will cause the " | + | After being successfully programmed, the FPGA will illuminate |
The following sections provide greater detail about programming the NetFPGA-SUME using the different methods available. | The following sections provide greater detail about programming the NetFPGA-SUME using the different methods available. | ||
Line 275: | Line 275: | ||
Bitstreams are programmed into or read from flash using the dsumecfg tool included with the Adept Utilities package. You can also use this tool to set the BSS register. The Adept Utilities toolset can be downloaded for free from the Adept 2 page on the [[http:// | Bitstreams are programmed into or read from flash using the dsumecfg tool included with the Adept Utilities package. You can also use this tool to set the BSS register. The Adept Utilities toolset can be downloaded for free from the Adept 2 page on the [[http:// | ||
- | * In order to use dsumecfg you must have the NetFPGA-SUME connected to your computer via the USB-JTAG port. | + | * In order to use dsumecfg, you must have the NetFPGA-SUME connected to your computer via the USB-JTAG port. |
* To decrease programming times, we highly recommend enabling bitstream compression in Vivado or ISE when you generate your bitstream. | * To decrease programming times, we highly recommend enabling bitstream compression in Vivado or ISE when you generate your bitstream. | ||
* dsumecfg will not work properly if an FMC card that inserts a JTAG device into the scan chain is attached to the NetFPGA-SUME. | * dsumecfg will not work properly if an FMC card that inserts a JTAG device into the scan chain is attached to the NetFPGA-SUME. | ||
Line 286: | Line 286: | ||
=== DDR3 SODIMM === | === DDR3 SODIMM === | ||
- | The NetFPGA-SUME board comes with two Micron MT8KTF51264HZ-1G9 4GB DDR3 SDRAM SODIMM which employs an 932.84MHz 64bit-wide data bus capable of operating at a data rate of 1866MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in Vivado Design Suite. The interface is automatically configured by the MIG for use with the AXI4 system bus and provide a fixed 4:1 memory to bus clock ratio. The input clock for both SDRAM SODIMMs is a 233MHz clock generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. The clock period of SDRAM is configured to 1177ps (849.62MHz), | + | The NetFPGA-SUME board comes with two Micron MT8KTF51264HZ-1G9 4GB DDR3 SDRAM SODIMM, which employs an 932.84MHz 64bit-wide data bus capable of operating at a data rate of 1866MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in Vivado Design Suite. The interface is automatically configured by the MIG for use with the AXI4 system bus and provide a fixed 4:1 memory to bus clock ratio. The input clock for both SDRAM SODIMMs is a 233MHz clock generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. The clock period of SDRAM is configured to 1177ps (849.62MHz), |
=== QDRII+ SRAM === | === QDRII+ SRAM === | ||
- | Three Cypress CY7C25652KV18 Quad Data Rate II+ (QDRII+) SRAMs are provided for applications that require high speed, low latency memory. Each component provides a 36 bit wide data bus and has a density of 72 Megabits. Common applications include FIFO buffers and look-up tables. The notion of “Quad” data rate comes from the ability to simultaneously read from a unidirectional read port and write to a unidirectional write port on both clock edges. The QDRII+ SRAMs on NetFPGA-SUME board are capable of operating at up to 500MHz to yield data transfer rates of up to 1GT/s per 36-bit wide data bus. The Xilinx Memory Interface Generator (MIG) is able to generate and configure an native interface into the QDRII+ via the user friendly wizard tool. More information regarding the QDRII+ memory part and the Xilinx MIG tool can be found in the Cypress // | + | Three Cypress CY7C25652KV18 Quad Data Rate II+ (QDRII+) SRAMs are provided for applications that require high speed, low latency memory. Each component provides a 36 bit wide data bus and has a density of 72 Megabits. Common applications include FIFO buffers and look-up tables. The notion of "Quad" |
- | // data sheet, the Cypress Application Note //QDR-II, QDR-II+, DDR-II, DDR-II+ Design Guide (AN4065)//, and the //Xilinx 7 Series FPGAs Memory Interface Solutions User Guide (UG586)// | + | // data sheet, the Cypress Application Note //QDR-II, QDR-II+, DDR-II, DDR-II+ Design Guide (AN4065)//, and the //Xilinx 7-Series FPGAs Memory Interface Solutions User Guide (UG586)// |
- | QDRA and QDRB share FPGA bank 17, which means that in order to access them simultaneously a bank sharing solution must be used that extends beyond the default functionality of the MIG. This solution is still currently being developed. Please refer to //Xilinx Answer Record 41706// for further information. | + | QDRA and QDRB share FPGA bank 17, which means that in order to access them simultaneously, a bank sharing solution must be used that extends beyond the default functionality of the MIG. This solution is still currently being developed. Please refer to //Xilinx Answer Record 41706// for further information. |
==== Storage ==== | ==== Storage ==== | ||
Line 302: | Line 302: | ||
flash and configuring the FPGA from stored bitstreams, see the section titled " | flash and configuring the FPGA from stored bitstreams, see the section titled " | ||
- | === Micro-SD | + | === MicroSD |
- | The micro-SD | + | The microSD |
==== SATA ==== | ==== SATA ==== | ||
- | The NetFPGA-SUME board provides two SATA ports which are SATA-III compatible (6Gbps). Two GTX transceivers (Lane 0,1 on Bank 116) are dedicated to these two ports with a master clock of 150MHz generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. SATA PHY controller can be generated using Xilinx GTX Transceiver Wizard. Please refer to //Xilinx Answer Record AR 53364//, //AR 44587// and //UG769 7 Series FPGAs Transceivers Wizard v2.6 User Guide// for more information. | + | The NetFPGA-SUME board provides two SATA ports which are SATA-III compatible (6Gbps). Two GTX transceivers (Lane 0,1 on Bank 116) are dedicated to these two ports with a master clock of 150MHz generated by Discera DSC1103 Low Jitter Precision LVDS Oscillator. SATA PHY controller can be generated using Xilinx GTX Transceiver Wizard. Please refer to //Xilinx Answer Record AR 53364//, //AR 44587// and //UG769 7-Series FPGAs Transceivers Wizard v2.6 User Guide// for more information. |
==== PCI Express ==== | ==== PCI Express ==== | ||
- | The NetFPGA-SUME is designed with a PCI-Express form factor to support interconnection with common processor motherboards. Eight of the FPGA’s high speed serial GTX transceivers are dedicated to implementing eight-lanes of Gen. 3.0 (8 GB/s) PCIe communications with a host processing system (there is no support for Gen3 x4 configuration). These transceivers work in conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core. Please refer to the Xilinx 7 Series FPGAs Integrated Block for PCI Express V2.0 (PG054) product guide and 7 Series FPGAs GTX/GTH Transceivers (UG476) user guide for more information. | + | The NetFPGA-SUME is designed with a PCI-Express form factor to support interconnection with common processor motherboards. Eight of the FPGA's high speed serial GTX transceivers are dedicated to implementing eight-lanes of Gen. 3.0 (8 GB/s) PCIe communications with a host processing system (there is no support for Gen3 x4 configuration). These transceivers work in conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core. Please refer to the Xilinx |
Line 353: | Line 353: | ||
Please refer to the American National Standards Institute ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard for | Please refer to the American National Standards Institute ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard for | ||
- | additional | + | additional |
- | constraints relating FPGA pins to their associated FMC control and connector pins. | + | |
=== QTH === | === QTH === | ||
Line 362: | Line 361: | ||
=== Pmod === | === Pmod === | ||
- | {{ : | + | {{ : |
- | The NetFPGA-SUME board also provides a Pmod Connector | + | The NetFPGA-SUME board also provides a Pmod port for peripheral extension. The Pmod port is arranged |
- | Please note that the signals on Pmod connector is connected to FPGA via two 4-bit dual-supply bus transceivers (IC1/2 SN74AVC4T774) with configurable voltage translation and 3-state outputs. You need to specifically set DIR for each pins to control the signal direction. The bus transceiver is enabled by driving OE pin of the bus transceiver low. | + | The signals on the Pmod port are connected to the FPGA via two 4-bit dual-supply bus transceivers (IC1 and IC2, part number |
==== Basic I/O ==== | ==== Basic I/O ==== | ||
Line 373: | Line 372: | ||
The two LEDs are green and are illuminated when driven high. It is possible to control the brightness by providing a pulse width modulated signal that varies the duty cycle from 0% to 100%. | The two LEDs are green and are illuminated when driven high. It is possible to control the brightness by providing a pulse width modulated signal that varies the duty cycle from 0% to 100%. | ||
- | An additional pushbutton (BTN3) is attached to the PROGRAM_B pin of the Virtex-7 FPGA. Pressing this button will clear the configuration inside the FPGA and cause the DONE pin to go low. If the mode jumper is not shorted, this will also trigger the CPLD to reprogram the FPGA with a bitstream stored in flash (See the "FPGA Configuration" | + | An additional |
LD4 is attached to the DONE pin of the FPGA, and is illuminated whenever the FPGA is configured with a valid bitstream. | LD4 is attached to the DONE pin of the FPGA, and is illuminated whenever the FPGA is configured with a valid bitstream. |