Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
Last revisionBoth sides next revision
reference:instrumentation:zmoddac:reference-manual [2019/10/22 07:38] – [5. The SYZYGY™ Connector] Mircea Dabacanreference:instrumentation:zmoddac:reference-manual [2019/11/04 07:36] – [2.4. AWG Out] Mircea Dabacan
Line 19: Line 19:
   * Channel type: single ended   * Channel type: single ended
   * Resolution: 14-bit   * Resolution: 14-bit
-  * Absolute Resolution (amplitude ≤1.25V): 152μV +  * Absolute Resolution (amplitude ≤1.25V): 167μV 
-  * Absolute Resolution (amplitude >1.25V): 610μV+  * Absolute Resolution (amplitude >1.25V): 665μV
   * Accuracy - typical (|Vout| ≤ 1.25V): ±10mV ± 0.5% FIXME   * Accuracy - typical (|Vout| ≤ 1.25V): ±10mV ± 0.5% FIXME
   * Accuracy - typical (|Vout| > 1.25V): ±25mV ± 0.5% FIXME   * Accuracy - typical (|Vout| > 1.25V): ±25mV ± 0.5% FIXME
 +  * Output impedance: 50Ω
   * Sample rate (real time): 100MS/s.   * Sample rate (real time): 100MS/s.
   * AC amplitude (max): ±5 V.    * AC amplitude (max): ±5 V. 
Line 78: Line 79:
 ==== 2.2. AWG DAC ==== ==== 2.2. AWG DAC ====
  
-The Analog Devices [[http://www.analog.com/en/digital-to-analog-converters/high-speed-da-converters/ad9717/products/product.html|AD9717]] dual, low-power 14-bit TxDAC digital-to-analog converter is used to generate the wave [[reference:instrumentation:zmoddac:reference-manual#figure_4|Fig. 4]]. The main features are:+The Analog Devices [[http://www.analog.com/en/digital-to-analog-converters/high-speed-da-converters/ad9717/products/product.html|AD9717]] dual, low-power 14-bit TxDAC digital-to-analog converter is used to generate the wave. The main features are:
   * Power dissipation @ 3.3V, 2 mA output: 86 mW @ 125MS/s, sleep mode: <3 mW @ 3.3V    * Power dissipation @ 3.3V, 2 mA output: 86 mW @ 125MS/s, sleep mode: <3 mW @ 3.3V 
   * Supply voltage: 1.8V to 3.3V    * Supply voltage: 1.8V to 3.3V 
Line 101: Line 102:
 For high-gain: For high-gain:
  
-$$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{8k \Omega}=4mA\label{3}\tag{3}$$+$$I_{outAWGFS\_HG}=32 \cdot \frac{1V}{8.06k \Omega}=3.97mA\label{3}\tag{3}$$
  
 For low-gain: For low-gain:
Line 141: Line 142:
  
  
-The Voltage range extends between:+The IC5B output voltage range extends between:
  
 $$ - V_{OUT\;IC5B\;FS} \le V_{OUT\;IC5B} <  - V_{OUT\;IC5B\;FS}\label{7}\tag{7}$$ $$ - V_{OUT\;IC5B\;FS} \le V_{OUT\;IC5B} <  - V_{OUT\;IC5B\;FS}\label{7}\tag{7}$$
Line 147: Line 148:
 Where (for high gain, respectively, low gain): Where (for high gain, respectively, low gain):
  
-$$V_{OUT\;IC5B\;FS\;HG}=I_{outAWG\;FS\;HG} \cdot R_{44}=996mV$$+$$V_{OUT\;IC5B\;FS\;HG}=I_{outAWG\;FS\;HG} \cdot R_{44}=989mV$$
 $$V_{OUT\;IC5B\;FS\;LG}=I_{outAWG\;FS\;LG} \cdot R_{44}=249mV\label{8}\tag{8}$$ $$V_{OUT\;IC5B\;FS\;LG}=I_{outAWG\;FS\;LG} \cdot R_{44}=249mV\label{8}\tag{8}$$
  
  
 {{:reference:instrumentation:zmoddac:zmoddacivandout.png?w=750&}}  {{:reference:instrumentation:zmoddac:zmoddacivandout.png?w=750&}} 
 +{{:reference:instrumentation:zmoddac:zmoddacrel.png?w=750&}} 
 +
 +{{:reference:instrumentation:zmoddac:zmoddacreldriver.png?w=300&}} 
 +
 {{:reference:instrumentation:zmoddac:zmoddacivdecoupling.png?w=600&}}  {{:reference:instrumentation:zmoddac:zmoddacivdecoupling.png?w=600&}} 
 {{:reference:instrumentation:zmoddac:zmoddacoutdecoupling.png?w=700&}}  {{:reference:instrumentation:zmoddac:zmoddacoutdecoupling.png?w=700&}} 
Line 176: Line 181:
 $$V_{AWG\;REL}=V_{OUT\;IC5B} \cdot (1+\frac{R_{41}}{R_{42}})=5.51 \cdot V_{OUT\;IC5B}\label{9}\tag{9}$$ $$V_{AWG\;REL}=V_{OUT\;IC5B} \cdot (1+\frac{R_{41}}{R_{42}})=5.51 \cdot V_{OUT\;IC5B}\label{9}\tag{9}$$
  
-The output voltage range depends on High- versus Lowe-range:+The output voltage range depends on High-gain versus Low-gain selection:
  
-$$ - 5.49V <  - 5V < V_{AWG\;REL\;HG} < 5V < 5.49V$$+$$ - 5.49V <  - 5V < V_{AWG\;REL\;HG} < 5V < 5.45V$$
 $$ - 1.37V < 1.25V < V_{AWG\;REL\;LG} < 1.25V < 1.37V\label{10}\tag{10}$$ $$ - 1.37V < 1.25V < V_{AWG\;REL\;LG} < 1.25V < 1.37V\label{10}\tag{10}$$
  
  
-Low-gain is used to generate low amplitude signals with improved accuracy. Any amplitude of the output signal is derivable by combining LowGain/HighGain setting (rough) with the digital signal amplitude (fine).+Low-gain is used to generate low amplitude signals with improved accuracy. Any amplitude of the output signal can be generated by combining LowGain/HighGain setting (rough) with the digital signal amplitude (fine).
  
 With the 14-bit DAC, the absolute resolution of the AWG AC component is: With the 14-bit DAC, the absolute resolution of the AWG AC component is:
  
 $$at\;Low\;Gain:\;\;\;\frac{{2.74V}}{{{2^{14}}}} = 167\mu V$$ $$at\;Low\;Gain:\;\;\;\frac{{2.74V}}{{{2^{14}}}} = 167\mu V$$
-$$at\;High\;Gain:\;\;\;\;\;\frac{{10.98V}}{{{2^{14}}}} = 670\mu V\label{11}\tag{11}$$+$$at\;High\;Gain:\;\;\;\;\;\frac{{10.9V}}{{{2^{14}}}} = 665\mu V\label{11}\tag{11}$$
  
-AD8021 is supplied with $\pm 8V$; to avoid saturation the user should keep the voltage in \ref{10} to:+AD8021 is supplied with +8.5V/-8V (the VCC8V0 voltage is in fact 8.5V). Conform to the data sheet, the worst case output voltage swing is V<sub>-</sub>+1.8V to V<sub>+</sub>-2.2V.
  
-$$ - 6.5V < 5V < V_{AWG\;REL} < 5V < 6.2V\label{12}\tag{12}$$+The nominal resistance of the PTC in the feedback loop is 33 ohm. The maximum current delivered by te AWG is 30mA. 
 + 
 +To avoid saturation, the voltage in \ref{9} should stay in: 
 + 
 +$$ -8V + 1.8V + 33\Omega *30mA = -5.21V < -5V < V_{AWG\;REL} < 5V < 8.5-2.2V-33\Omega*30mA = 5.31V\label{12}\tag{12}$$
  
 Only inner (tighter) ranges are used in equations \ref{10} and \ref{12}, for providing tolerance margins. Only inner (tighter) ranges are used in equations \ref{10} and \ref{12}, for providing tolerance margins.
Line 209: Line 218:
     * 4 * 1.33  = 5.32 (for HG: +/-5V)     * 4 * 1.33  = 5.32 (for HG: +/-5V)
  
-The R146 PTC thermistor provides thermal protection in case of an output shortcut.+The R146 PTC thermistor provides thermal protection in case of an output short-circuit. 
 + 
 +The IC7 relay (non-latching) is OPEN at the power-on, decoupling the power-on glitch of the OpAmp from the load. It is CLOSED by the FPGA, via Q1.   
 +R37 is a pull down when IC7 is OPEN and a dummy load when IC7 is CLOSED. 
 +D2 is an ESD suppressor.  
 + 
 +R36 is the 50Ω AWG output impedance. 
 ---- ----
 ==== 2.3. AWG output stage protection ==== ==== 2.3. AWG output stage protection ====
Line 227: Line 242:
 The protection circuit in [[reference:instrumentation:zmoddac:reference-manual#figure_6|Fig. 6]] limit the Output stage supply currents, with fold-back: The protection circuit in [[reference:instrumentation:zmoddac:reference-manual#figure_6|Fig. 6]] limit the Output stage supply currents, with fold-back:
  
-$$\frac {AVCC8V0 \cdot R_{77}}{R_{72}+R_{77}} = \frac{(AVCC8V0 + R_{70} \cdot I_{out}) \cdot R_{74}+$$\frac {AVCC8V0 \cdot R_{77}}{R_{72}+R_{77}} = \frac{(AVCC8V0 - R_{70} \cdot I_{out}) \cdot R_{74}+
 AVCC8V0AWG1 \cdot R_{73}}{R_{73}+R_{74}}$$ AVCC8V0AWG1 \cdot R_{73}}{R_{73}+R_{74}}$$
  
Line 249: Line 264:
 ==== 2.5. AWG Spectral Characteristics ==== ==== 2.5. AWG Spectral Characteristics ====
  
-For Low frequency range, the spectral characteristic was traced by a network analyzer function, with the ZmodDAC connected to a ZmodADC, as shown in [[reference:instrumentation:zmoddac:reference-manual#figure_7|Fig. 7]]. Since the ZmodADC BW is much wider, the overall system frequency characteristic represents the ZmodDAC characteristic. The BW is flat within 0.1dB up tp 10MHz+.+For low frequency range, the spectral characteristic was traced by a network analyzer function, with the ZmodDAC connected to a ZmodADC, as shown in [[reference:instrumentation:zmoddac:reference-manual#figure_7|Fig. 7]]. Since the ZmodADC BW is much wider, the overall system frequency characteristic represents the ZmodDAC characteristic. The BW is flat within 0.1dB up tp 10MHz+.
  
 {{:reference:instrumentation:zmoddac:WFZmodDAC_BW.png?w=450&}}  {{:reference:instrumentation:zmoddac:WFZmodDAC_BW.png?w=450&}} 
Line 258: Line 273:
  
 To trace the  analog bandwidth of the DAC and output stage beyond the theoretical limit of f<sub>SAMPLE</sub>/2= 50MHz, the following experiment was performed: To trace the  analog bandwidth of the DAC and output stage beyond the theoretical limit of f<sub>SAMPLE</sub>/2= 50MHz, the following experiment was performed:
-  * The AWG was set to generate a 20MGz rectangular signal, 100mV amplitude;+  * The AWG was set to generate a 2MHz rectangular signal, 100mV amplitude;
   * the theoretical amplitudes of the fundamental and first 69 harmonics was computed;   * the theoretical amplitudes of the fundamental and first 69 harmonics was computed;
-  * the actual amplitudes of the fundamental and first 69 harmonics was measured with a high sapling rate scope (10GSPS, 2GHz BW);+  * the actual amplitudes of the fundamental and first 69 harmonics were measured with a high sampling rate scope (10GSPS, 2GHz BW);
   * the dB difference between the theoretical and measured amplitudes was plotted. This represents an approximation of the frequency characteristic of the DAC and output stage.   * the dB difference between the theoretical and measured amplitudes was plotted. This represents an approximation of the frequency characteristic of the DAC and output stage.
  
Line 272: Line 287:
  
 The 3dB bandwidth is close to the theoretical Nyquist limit for a 100MHz sampling system. This has the advantage of very sharp edges (see the rectangular signal in [[reference:instrumentation:zmoddac:reference-manual#figure_9|Fig. 9]]), but also generates alias effects. The ZmodADC generated signals were recorded with a high BW scope in [[reference:instrumentation:zmoddac:reference-manual#figure_9|Fig. 9]], and  The 3dB bandwidth is close to the theoretical Nyquist limit for a 100MHz sampling system. This has the advantage of very sharp edges (see the rectangular signal in [[reference:instrumentation:zmoddac:reference-manual#figure_9|Fig. 9]]), but also generates alias effects. The ZmodADC generated signals were recorded with a high BW scope in [[reference:instrumentation:zmoddac:reference-manual#figure_9|Fig. 9]], and 
- the right side of [[reference:instrumentation:zmoddac:reference-manual#figure_10|Fig. 10]] and [[reference:instrumentation:zmoddac:reference-manual#figure_11|Fig. 11]]. In [[reference:instrumentation:zmoddac:reference-manual#figure_11|Fig. 11]], the sinus frequency is 10MHz, and the 100MHz samples are clearly visible. In the left side of [[reference:instrumentation:zmoddac:reference-manual#figure_10|Fig. 10]] and [[reference:instrumentation:zmoddac:reference-manual#figure_11|Fig. 11]], the same scope was used but with 20MHz BW limitation. The rectangular signal edges are slower and the sinus samples are not visible.+ the right side of [[reference:instrumentation:zmoddac:reference-manual#figure_10|Fig. 10]] and [[reference:instrumentation:zmoddac:reference-manual#figure_11|Fig. 11]]. In [[reference:instrumentation:zmoddac:reference-manual#figure_11|Fig. 11]], the sinus frequency is 10MHz, and the 100MHz samples are clearly visible. In the left side of [[reference:instrumentation:zmoddac:reference-manual#figure_10|Fig. 10]] and [[reference:instrumentation:zmoddac:reference-manual#figure_11|Fig. 11]], the same scope was used, but with 20MHz BW limitation. The rectangular signal edges are slower and the sine wave samples are not visible.
  
 The typical Slew Rate of the AWG can be read in [[reference:instrumentation:zmoddac:reference-manual#figure_9|Fig. 9]]: The typical Slew Rate of the AWG can be read in [[reference:instrumentation:zmoddac:reference-manual#figure_9|Fig. 9]]:
Line 294: Line 309:
 ===== 3. MCU ===== ===== 3. MCU =====
  
-The [[https://www.microchip.com/wwwproducts/en/ATTINY44A|ATtinny44]] MCU in [[reference:instrumentation:zmodadc:reference-manual#figure_12|Fig. 12]] works as a I2C memory, storing the SYZYGY™ DNA information and the Calibration Coefficients. The J5 connector is used for programming the MCU and the SYZYGY™ DNA at manufacturing. +The [[https://www.microchip.com/wwwproducts/en/ATTINY44A|ATtinny44]] MCU works as a I2C memory, storing the SYZYGY™ DNA information and the Calibration Coefficients. The J5 connector is used for programming the MCU and the SYZYGY™ DNA at manufacturing. 
  
 The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as "read-only". The User Calibration Coefficients are stored in the EEPROM memory of the MCU, which is write-protected via a magic number at a magic address. The memory structure can be consulted below. The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as "read-only". The User Calibration Coefficients are stored in the EEPROM memory of the MCU, which is write-protected via a magic number at a magic address. The memory structure can be consulted below.
Line 361: Line 376:
 ==== 3.2. Calibration Memory ==== ==== 3.2. Calibration Memory ====
  
-The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, capacitance, offsets, bias currents, etc.) as typical values and tolerances. The equations in previous chapters consider typical values. Component tolerances affect DC and AC performances of the Zmod ADC. To minimize these effects, the design uses:+The analog circuitry described in previous chapters includes passive and active electronic components. The datasheet specs show parameters (resistance, capacitance, offsets, bias currents, etc.) as typical values and tolerances. The equations in previous chapters consider typical values. Component tolerances affect DC and AC performances of the Zmod DAC. To minimize these effects, the design uses:
  
   * 0.1% resistors and 1% capacitors in all the critical analog signal paths   * 0.1% resistors and 1% capacitors in all the critical analog signal paths
Line 369: Line 384:
   * User software calibration, as an option   * User software calibration, as an option
  
-A software calibration is performed on each device as a part of the manufacturing test. Reference signals are connected to the Scope inputs. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Zmod ADC device, as Factory Calibration. The WaveForms software allows the user performing an in-house calibration and overwrite the Calibration Data. Returning to Factory Calibration is always possible.+A software calibration is performed on each device as a part of the manufacturing test. The AWG outputs are connected to calibrated voltmeters. A set of measurements is used to identify all the DC errors (Gain, Offset) of each analog stage. Correction (Calibration) parameters are computed and stored in the Calibration Memory, on the Zmod DAC device, both as Factory Calibration Data and User Calibration Data. The WaveForms software allows the user performing an in-house calibration and overwrite the User Calibration Data. Returning to Factory Calibration is always possible.
  
- +The Software reads the calibration parameters from the Zmod DAC MCU via the I2C bus and uses them to correct the generated signals. The structure of the data is shown below:
-The Software reads the calibration parameters from the Zmod ADC MCU via the I2C bus and uses them to correct the acquired signals. The structure of the data is shown below:+
  
 //{{anchor:table_3:Table 3. The Calibration Data Structure}}// //{{anchor:table_3:Table 3. The Calibration Data Structure}}//
Line 404: Line 418:
  
 ---- ----
- 
- 
 ===== 4. Power Supplies ===== ===== 4. Power Supplies =====
  
Line 425: Line 437:
 ==== 4.1. AVCC3V3 ==== ==== 4.1. AVCC3V3 ====
  
-The analog supply AVCC3V3 is built from VCC5V0 using IC10, an [[https://www.analog.com/en/products/adp122.html|ADP122]] 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Fixed Output Voltage. To reduce noise in the I/V stage, the rail uses the LC filter: FB5 in [[reference:instrumentation:zmodadc:reference-manual#figure_8|Fig. 8]], FB6 (Channel 2 ADC Driver - not shown), FB7 in [[reference:instrumentation:zmodadc:reference-manual#figure_7|Fig. 7]]. +The analog supply AVCC3V3 is built from VCC5V0 using IC10, an [[https://www.analog.com/en/products/adp122.html|ADP122]] 5.5 V Input, 300 mA, Low Quiescent Current, CMOS Linear Regulator, Fixed Output Voltage. To reduce noise in the I/V stage, the rail uses the LC filter: FB5 in [[reference:instrumentation:zmoddac:reference-manual#figure_5|Fig. 5]].  
   * Input voltage supply range: 2.3 V to 5.5 V   * Input voltage supply range: 2.3 V to 5.5 V
   * 300 mA maximum output current   * 300 mA maximum output current
Line 448: Line 459:
 ==== 4.2. AVCC-2V5 ==== ==== 4.2. AVCC-2V5 ====
  
-The AVCC-2V5 analog power supply is implemented with the [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp2301/products/product.html|ADP2301]] Step-Down regulator in an inverting Buck-Boost configuration. See application Note [[http://www.analog.com/static/imported-files/application_notes/AN-1083.pdf|AN-1083: Designing an Inverting Buck Boost Using the ADP2300 and ADP2301]]. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses individual LC filters: FB1 in [[reference:instrumentation:zmoddac:reference-manual#figure_15|Fig. 15]], FB4 (Channel 2 ADC Buffer - not shown). The ADP2301 features:+The AVCC-2V5 analog power supply is implemented with the [[http://www.analog.com/en/power-management/switching-regulators-integrated-fet-switches/adp2301/products/product.html|ADP2301]] Step-Down regulator in an inverting Buck-Boost configuration. See application Note [[http://www.analog.com/static/imported-files/application_notes/AN-1083.pdf|AN-1083: Designing an Inverting Buck Boost Using the ADP2300 and ADP2301]]. To reduce noise and reduce the crosstalk between supplied circuits, the rail uses the LC filter: FB3 in [[reference:instrumentation:zmoddac:reference-manual#figure_5|Fig. 5]].. The ADP2301 features:
  
   * 1.2 A maximum load current    * 1.2 A maximum load current 
Line 475: Line 486:
 ==== 4.3. AVCC8V0 ==== ==== 4.3. AVCC8V0 ====
  
-The user power supplies [[reference:instrumentation:zmoddac:reference-manual#figure_15|Fig. 15]] use [[https://www.analog.com/en/products/adp1612.html|ADP1612]] Switching Converter in Buck-Boost DC-to-DC topology. Main features:+The user power supplies [[reference:instrumentation:zmoddac:reference-manual#figure_15|Fig. 15]] use [[https://www.analog.com/en/products/adp1612.html|ADP1612]] Switching Converter in SEPIC DC-to-DC topology. Main features:
  
   * 1.4A current limit   * 1.4A current limit
Line 495: Line 506:
 $${V_{FB}} = 1.235V\;typical\label{22}\tag{22}$$ $${V_{FB}} = 1.235V\;typical\label{22}\tag{22}$$
  
-Each supply is enabled after VCC5V0 and AVCC3V3 (see EN_AVCC in [[reference:instrumentation:zmoddac:reference-manual#figure_15|Fig. 15]])+The supply is enabled after VCC5V0 and AVCC3V3 (see EN_AVCC in [[reference:instrumentation:zmoddac:reference-manual#figure_16|Fig. 16]])
  
 ---- ----
 ==== 4.4. AVCC-8V0 ==== ==== 4.4. AVCC-8V0 ====
  
-The user power supplies [[reference:instrumentation:zmoddac:reference-manual#figure_15|Fig. 15]] use [[https://www.analog.com/en/products/adp1612.html|ADP1612]] Switching Converter in Buck-Boost DC-to-DC topology. +The user power supplies [[reference:instrumentation:zmoddac:reference-manual#figure_16|Fig. 16]] use [[https://www.analog.com/en/products/adp1612.html|ADP1612]] Switching Converter in CUK DC-to-DC topology. 
  
 IC13 introduces the required inversion for the negative supply. [[https://www.analog.com/en/products/ada4841-1.html|ADA4841]] features: IC13 introduces the required inversion for the negative supply. [[https://www.analog.com/en/products/ada4841-1.html|ADA4841]] features: