Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revisionPrevious revision
Next revision		Previous revision
Next revisionBoth sides next revision
reference:programmable-logic:usb104a7:reference-manual [2020/08/24 19:18] – Arthur Brownprogrammable-logic:usb104a7:reference-manual [2021/05/14 23:07] – ↷ Links adapted because of a move operation Arthur Brown
Line 251: Line 251:
 Microblaze support for DPTI is provided by the AXI DPTI IP core which can be found in the [[https://github.com/Digilent/vivado-library|vivado-library]] repository on Digilent's GitHub. Microblaze support for DPTI is provided by the AXI DPTI IP core which can be found in the [[https://github.com/Digilent/vivado-library|vivado-library]] repository on Digilent's GitHub.
  
-The Digilent Adept Runtime can be used with the the Digilent Adept API in order to simplify the host side communication through DPTI. The Adept Runtime can be downloaded through the [[reference:software:adept:start|Adept]] wiki page. The Zmod ADC and Zmod DAC example projects, which can be found on the [[start|USB104 A7 Resource Center]] include example PC-side applications intended for receiving and transmitting data through the DPTI interface.+The Digilent Adept Runtime can be used with the the Digilent Adept API in order to simplify the host side communication through DPTI. The Adept Runtime can be downloaded through the [[software:adept:start|Adept]] wiki page. The Zmod ADC and Zmod DAC example projects, which can be found on the [[start|USB104 A7 Resource Center]] include example PC-side applications intended for receiving and transmitting data through the DPTI interface.
  
 **Note:** //A DSPI interface is also connected, but no demos are provided as of time of writing. Since the interfaces share pins, DPTI and DSPI cannot be used simultaneously. The pulldown resistor on the SPI enable line means that the default interface is DPTI. SPIEN should be held low or not be driven by the FPGA while using DPTI.// **Note:** //A DSPI interface is also connected, but no demos are provided as of time of writing. Since the interfaces share pins, DPTI and DSPI cannot be used simultaneously. The pulldown resistor on the SPI enable line means that the default interface is DPTI. SPIEN should be held low or not be driven by the FPGA while using DPTI.//
Line 288: Line 288:
 A SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Bank 15 of the FPGA is dedicated to the Zmod port and is powered by a dedicated adjustable rail, configured by the Platform MCU as the USB104 A7 is powered on. Template constraints for the Zmod port can be found in the USB104 A7's Master XDC file, available through Digilent's [[https://github.com/Digilent/digilent-xdc|digilent-xdc]] repository on Github. A SYZYGY Standard interface contains 16 single-ended I/O pins, 8 differential I/O pairs (which can alternatively be used as 16 additional single-ended I/O pins), and two dedicated differential clocks - one for input and one for output. Bank 15 of the FPGA is dedicated to the Zmod port and is powered by a dedicated adjustable rail, configured by the Platform MCU as the USB104 A7 is powered on. Template constraints for the Zmod port can be found in the USB104 A7's Master XDC file, available through Digilent's [[https://github.com/Digilent/digilent-xdc|digilent-xdc]] repository on Github.
  
-Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[reference:zmod:start|Digilent Zmod]]. Demos are available for the Zmod ADC and the Zmod DAC on the USB104 A7's [[start|Resource Center]].+Digilent provides Eclypse-compatible low-level IPs, scripted Vivado flows, and software libraries to support each [[zmod:start|Digilent Zmod]]. Demos are available for the Zmod ADC and the Zmod DAC on the USB104 A7's [[start|Resource Center]].
  
 For more information on the SYZYGY standard, see [[https://syzygyfpga.io/|syzygyfpga.io]]. For more information on the SYZYGY standard, see [[https://syzygyfpga.io/|syzygyfpga.io]].