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learn:programmable-logic:tutorials:zedboard-led-demo:start [2016/07/29 23:22] – jon peyronlearn:programmable-logic:tutorials:zedboard-led-demo:start [2017/12/07 21:40] – [Tutorial] jon peyron
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 >1.6) Select **Boards** and select the **Zedboard** board file. Click **Next** and then **Finish**. >1.6) Select **Boards** and select the **Zedboard** board file. Click **Next** and then **Finish**.
 >  > 
->{{:reference:programmable-logic:zedboard-getting-started-with-zynq:image_6.jpg?600|}}+>{{:learn:programmable-logic:tutorials:zedboard-getting-started-with-zynq:board_file_zedboard.jpg?600|}} 
 + 
 +<WRAP center round tip 60%>  
 +Make sure to select the board file made by Digilent. 
 +</WRAP>
 ----- -----
 +
 ==== 2. Creating a New Block Design ==== ==== 2. Creating a New Block Design ====
  
Line 124: Line 129:
 >{{:zybo:blank_block_design.png?700|}} >{{:zybo:blank_block_design.png?700|}}
  
 +----
  
 +==== 3. Adding Our Custom IP Repo ====
 +
 +>3.1) Find and click **"Project Settings"** under Project Manager on the left side of Vivado.
 +>
 +>{{:arty:projsetting.jpg?300|}}
 +
 +>3.2) Within project settings, click "IP" on the left side. Then click the "Repository Manager" tab and click the + button (Highlighted below).
 +>
 +>{{:arty:iprepo.jpg?500|}}
 +
 +>3.3) Navigate to your projects folder and select the **"DigiLED-master"** folder.
 +>
 +>{{:arty:iprepo2.jpg?200|}}
 +
 +>3.4) Verify that the new repo is in the list and click OK to exit project settings.
 +>
 +>{{:arty:iprepo3.jpg?500|}}
 +
 +=== 4. Adding Our Custom IP ===
 +
 +>4.1) Click the {{:genesys2:addip.jpg?nolink|}}**"Add IP"** button. Type "DigiLED" in the search box and double click **"DigiLED_v1.0"**. This will add our custom IP to the block design.
 +>
 +>{{:arty:addip2.jpg?300|}}
 +
 +>4.2) Click {{:genesys2:addip.jpg?nolink|}}**"Add IP"** button again. This time type "Zynq" in the search box and double click **ZYNQ7 Processing System**.
 +>
 +>{{:zybo:2.jpg?direct&300|}}
 +>
 +>This will add the Zynq processor to our block design.
 +>
 +>{{:zybo:3.jpg?direct&500|}}
 +
 +>4.3) Click **"Run Block Automation"** and click **OK** to auto configure the Zynq core.
 +>
 +>{{:zybo:4.jpg?direct&500|}}
 +
 +>4.4) Click run **Run Connection Automation** and click **OK** to connect the DigiLED to the Zynq core.
 +>
 +>{{:zybo:5.jpg?direct&600|}}
 +
 +-----
 +
 +==== 5. Configuring the IP ====
 +
 +>5.1) Find the **DigiLED_0** block and double click the block to customize it.
 +>
 +>{{:arty:block.jpg?300|}}
 +
 +>5.2) Select the **HSV** Bullet and change the Number of LEDs field to the number of LEDs on your RGB LED strip before clicking OK.
 +>
 +>{{:arty:custom.jpg?500|}}
 +
 +-----
 +
 +==== 6. Adding the LED Signal Pin ====
 +
 +>6.1) Right click within your block design and click **"Create Port"**
 +>
 +>{{:arty:createport.jpg?300|}}
 +
 +>6.2) Name the port "led_pin" and set it as an **Output**. Click OK.
 +>
 +>{{:arty:led_pin.jpg?500|}}
 +
 +>6.3) Connect the "led_pin" to "led_out" on the DigiLED_0 block using your cursor (It will look like a pencil).
 +>
 +>{{:zybo:6.jpg?direct&600|}}
 +
 +>6.4) On the left of your block design, select the **Sources** tab, and right click in the window. Select **Add Sources...** and a window will open. Select **Add or create constraints** and click **Next**.
 +>
 +>{{:zybo:7.jpg?direct&500|}}
 +>
 +>**Create a new file**, making sure the name has //no spaces//, and click **Finish**.
 +
 +
 +>6.5) In the sources window, open the constraints folder to find your new .xdc file. Open it.
 +>
 +>{{:zybo:8.jpg?direct&300|}}
 +
 +>6.6) Copy the line below, and paste it within pins.xdc. This is the pin connected to Connector JB1.
 +>
 +      set_property -dict { PACKAGE_PIN W12  IOSTANDARD LVCMOS33 } [get_ports { led_pin }];
 +
 +>6.7) Save pins.xdc and close it.
 +
 +>6.8) Right click **system.bd** and click **Create HDL Wrapper...**
 +>
 +>{{:arty:creathdl.jpg?300|}}
 +
 +----
 +
 +==== 7. Generating Bit File ====
 +
 +>7.1) In the top toolbar, click **Generate Bitstream**. If you haven't already saved your design, you will get a prompt to save the block design. 
 +>
 +>{{:arty:genbit.jpg?500|}}
 +
 +>7.2) After the bitstream has been generated, a message prompt will pop-up on the screen. You don't have to open the Implemented Design for this demo. Just click on Cancel. 
 +>
 +>{{:vivado:mig_42.jpg?500|}}
 +
 +==== 8. Exporting Hardware Design to SDK ====
 +
 +>8.1) On the top left corner of the window, from the tool bar click on //File// and select //Export Hardware//.
 +This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.
 +>**Make sure the generated bitstream is included by checking the box**.
 +>
 +>{{:vivado:mig_43.jpg?500|}}
 +
 +
 +----
 +
 +==== 9. Launching SDK ====
 +
 +>9.1) Go to //File// and select //Launch SDK// and click OK. The SDK file created local to the Vivado design project location will be launched. The hand-off to SDK from Vivado is complete. 
 +>
 +>{{:vivado:mig_45.jpg?500|}}
 +
 +----
 +
 +==== 10. Inside SDK for Vivado ====
 +
 +>10.1) A new window for SDK will open. The HW design specification and included IP blocks are displayed in the //system.hdf// file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory. 
 +>
 +>Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK. 
 +>
 +>Since we do not have any HW design edits at this point, we will proceed with creating a software application.
 +>
 +>{{:vivado:mig_46.jpg?500|}}
 +
 +>10.2) On the left corner of the main SDK window, you will find the //Project Explorer// panel. Notice that there is a main project folder under the name **system_wrapper_hw_platform_0**.
 +>
 +>**system** is the name of your block design created in Vivado. This hardware platform has all the HW design definitions, IP interfaces that have been added, external output signal information and local memory address information.
 +>
 +>Say if at this point, you have closed SDK, made edits to your existing hardware design, and exported your design to SDK then after launching the SDK tool, you will find a new hardware platform called: **system_wrapper_hw_platform_1** in addition to the old HW design i.e. **system_wrapper_hw_platform_0**.
 +>
 +>{{:vivado:mig_47.jpg?500|}}
 +
 +----
 +
 +==== 11. Creating New Application Project in SDK ====
 +
 +>11.1) Go to //File// in the main tool bar and select **New Application Project**. A new project window will pop up. 
 +>Give your SDK project a name that has no empty spaces such as "DigiLEDs". Make sure the //Target Hardware// is the correct hardware design. In our case, it will be "system_wrapper_hw_platform_0". Click "Next".
 +>
 +>{{:arty:digileds.jpg?500|}}
 +
 +>11.2) Select **Empty Application** under //Available Templates// on the left panel and click Finish. 
 +>
 +>{{:arty:empty.jpg?500|}}
 +
 +>11.3) After completing the previous step, you will see two new folders in the //Project Explorer// panel. 
 +     **DigiLEDs** which contains all the binaries, .C and .H (Header) files
 +     **DigiLEDs_bsp** which is the board support folder 
 +**DigiLEDs** is our main working source folder. This also contains an important file shown here which is the "lscript.ld". This is a Xilinx auto generated linker script file.
 +>
 +>{{:arty:projectexp.jpg?500|}}
 +
 +----
 +
 +==== 12. Adding the Main Source File ====
 +
 +>12.1) Navigate to the "main.c" file.
 +
 +>12.2) Click and drag this main.c file into the **DigiLEDs/src** folder within Xilinx SDK. Choose to copy these source files into the project and click OK.
 +>
 +>{{:arty:import.jpg?800|}}
 +
 +==== 13. Programming FPGA with Bit File ====
 +
 +>13.1) Make sure that the Zedboard is turned on and connected to the host PC with the provided micro USB cable. 
 +>
 +>In the quick selection tool bar, you will find a symbol with a red arrow and three green square boxes. {{:arty:programfpga.jpg|}}
 +>
 +>Click on this symbol to open the Program FPGA window. 
 +>
 +>Make sure that the //Hardware Platform// is selected as **system_wrapper_hw_platform_0**. 
 +>
 +>In the software configuration box, under //ELF File to Initialize in Block RAM// column, the row option must read **bootloop**. If not, click on the row and select **bootloop**.
 +>
 +>Now click on Program. 
 +>
 +>{{:vivado:mig_53.jpg?500|}}
 +
 +----
 +
 +==== 14. Program the Zynq Processor ====
 +
 +>14.1) After the FPGA has been successfully programmed with the bit file, from the //Project Explorer// panel, right click on the **"DigiLEDs"** project folder. Go to **"Run As"** and select **"Launch on Hardware (System Debugger)"**
 +>
 +>{{:arty:program.jpg?500|}}
 +>
 +>Your Zedboard will then start the DigiLEDs Demo. Pressing Button 0 will cycle through three patterns on the RGB LED strip.
  
 +----
 +{{tag>learn programmable-logic zedboard}}