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| cmod_s6:cmod_s6:ref_manual [2015/08/28 19:06] – created Joshua Woldstad | cmod_s6:cmod_s6:ref_manual [2022/03/28 21:42] (current) – Update xilinx link Arthur Brown | ||
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| * 216Kbits of block RAM; | * 216Kbits of block RAM; | ||
| * 2 CMTs (4 DCMs and 2 PLLs). | * 2 CMTs (4 DCMs and 2 PLLs). | ||
| - | * Cmod S6 features include: | + | Cmod S6 features include: |
| * 16Mbyte Spansion Quad SPI Flash for storing FPGA configurations and/or user data; | * 16Mbyte Spansion Quad SPI Flash for storing FPGA configurations and/or user data; | ||
| * 46 FPGA GPIO signals brought to DIP pins; | * 46 FPGA GPIO signals brought to DIP pins; | ||
| Line 52: | Line 52: | ||
| The Spartan 6 LX4 FPGA includes 3,840 6-LUT logic cells, 4,800 flip-flops, 216Kb of block RAM, 8 DSP slices, and two clock management tiles, each with two DCMs and one PLL. The fabric can support internal clock speeds above | The Spartan 6 LX4 FPGA includes 3,840 6-LUT logic cells, 4,800 flip-flops, 216Kb of block RAM, 8 DSP slices, and two clock management tiles, each with two DCMs and one PLL. The fabric can support internal clock speeds above | ||
| 400MHz, allowing the Cmod S6 to host high-speed or complex designs. Please see the Spartan 6 user manual | 400MHz, allowing the Cmod S6 to host high-speed or complex designs. Please see the Spartan 6 user manual | ||
| - | available at [[http:// | + | available at [[https://www.xilinx.com|www.xilinx.com]] for more detailed information. |
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