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atlys:atlys:refmanual [2014/09/11 22:39] – [Table] Joshua Woldstadatlys:atlys:refmanual [2014/09/11 23:18] – [Audio (AC-97)] Joshua Woldstad
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 A board test/demonstration program is loaded into the SPI Flash during manufacturing. That configuration, also available on the Digilent webpage, can be used to demonstrate and check all of the devices and circuits on the Atlys board. A board test/demonstration program is loaded into the SPI Flash during manufacturing. That configuration, also available on the Digilent webpage, can be used to demonstrate and check all of the devices and circuits on the Atlys board.
  
 +----
  
 +====== EthernetPHY ======
 +
 +The Atlys board includes a Marvell Alaska Tri-mode PHY (the 88E1111) paired with a Halo HFJ11-1G01E RJ-45 connector. Both MII and GMII interface modes are supported at 10/100/1000 Mb/s. Default settings used at power-on or reset are:
 +
 +  * MII/GMII mode to copper interface
 +  * Auto Negotiation Enabled, advertising all speeds, preferring Slave
 +  * MDIO interface selected, PHY MDIO address = 00111
 +  * No asymmetric pause, no MAC pause, automatic crossover enabled
 +  * Energy detect on cable disabled (Sleep Mode disabled), interrupt polarity LOW
 +
 +The data sheet for the Marvell PHY is available from Marvell only with a valid NDA. Please contact Marvell for more PHY-specific information.
 +
 +EDK-based designs can access the PHY using either the xps_ethernetlite IP core for 10/100 Mbps designs, or the xps_ll_temac IP core for 10/100/1000 Mbps designs. 
 +
 +{{:atlys:atlys:eth1.png?400 |}}
 +
 +|  __**RXD Signals**__        ||  **__TXD Signals__**        ||
 +| RXD0:                 | G16  | TXD0:                 | H16  |
 +| RXD1:                 | H14  | TXD1:                 | H13  |
 +| RXD2:                 | E16  | TXD2:                 | K14  |
 +| RXD3:                 | F15  | TXD3:                 | K13  |
 +| RXD4:                 | F14  | TXD4:                 | J13  |
 +| RXD5:                 | E18  | TXD5:                 | G14  |
 +| RXD6:                 | D18  | TXD6:                 | H12  |
 +| RXD7:                 | D17  | TXD7:                 | K12  |
 +
 +The Atlys Base System Builder (BSB) support package automatically generates a test application for the Ethernet MAC; this can be used as a reference for creating custom designs. 
 +
 +ISE designs can use the IP Core Generator wizard to create a tri-mode Ethernet MAC controller IP core.
 +
 +----
 +
 +====== Video Input and Output (HDMI Ports) ======
 +
 +The Atlys board contains four HDMI ports, including two buffered HDMI input/output ports, one buffered HDMI output port, and one unbuffered port that can be input or output (generally used as an output port.) The three buffered ports use HDMI type A connectors, and the unbuffered port uses a type D connector loaded on the bottom side of the PCB immediately under the Pmod connector (the type D connector is much smaller than the type A). The data signals on the unbuffered port are shared with a Pmod connector. This limits signal bandwidth somewhat – the shared connector may not be able to produce or receive the highest frequency video signals, particularly with longer HDMI cables.
 +
 +Since the HDMI and DVI systems use the same TMDS signaling standard, a simple adaptor (available at most electronics stores) can be used to drive a DVI connector from either of the HDMI output ports. The HDMI connector does not include VGA signals, so analog displays cannot be driven.
 +
 +The 19-pin HDMI connectors include four differential data channels, five GND connections, a one-wire Consumer Electronics Control (CEC) bus, a two-wire Display Data Channel (DDC) bus that is essentially an I2C bus, a Hot Plug Detect (HPD) signal, a 5V signal capable of delivering up to 50mA, and one reserved (RES) pin. Of these, only the differential data channels and I2C bus are connected to the FPGA. All signal connections are shown in the table below.
 +
 +{{ :atlys:atlys:hdmi.png?500 |}}
 +
 +
 +|  **__HDMI Type A Connectors__**                                                              ||||| **__HDMI Type D__**                                                    |||
 +|  __** Pin/Signal**__                     || **__J1: IN__**  | **__J2: Out__**  | **__J3: IN__**  | **__Pin/Signal__**                                  || **__JA: BiDi__**  |
 +| 1:                               | D2+    | B12             | B8               | J16             | 1:                                          | HPD    | JP3*              |
 +| 2:                               | D2_S   | GND             | GND              | GND             | 2:                                          | RES    | VCCB2             |
 +| 3:                               | D2-    | A12             | A8               | J18             | 3:                                          | D2+    | N5                |
 +| 4:                               | D1+    | B11             | C7               | L17             | 4:                                          | D2_S   | GND               |
 +| 5:                               | D1_S   | GND             | GND              | GND             | 5:                                          | D2-    | P6                |
 +| 6:                               | D1-    | A11             | A7               | L18             | 6:                                          | D1+    | T4                |
 +| 7:                               | D0+    | G9              | D8               | K17             | 7:                                          | D1_S   | GND               |
 +| 8:                               | D0_S   | GND             | GND              | GND             | 8:                                          | D1-    | V4                |
 +| 9:                               | D0-    | F9              | C8               | K18             | 9:                                          | D0+    | R3                |
 +| 10:                              | Clk+   | D11             | B6               | H17             | 10:                                         | D0_S   | GND               |
 +| 11:                              | Clk_S  | GND             | GND              | GND             | 11:                                         | D0-    | T3                |
 +| 12:                              | Clk-   | C11             | A6               | H18             | 12:                                         | Clk+   | T9                |
 +| 13:                              | CEC    | NC              | 0K to Gnd        | NC              | 13:                                         | Clk_S  | GND               |
 +| 14:                              | RES    | NC              | NC               | NC              | 14:                                         | Clk-   | V9                |
 +| 15:                              | SCL    | C13             | D9               | M16             | 15:                                         | CEC    | VCCB2             |
 +| 16:                              | SDA    | A13             | C9               | M18             | 16:                                         | Gnd    | GND               |
 +| 17:                              | Gnd    | GND             | GND              | GND             | 17:                                         | SCL    | C13¹              |
 +| 18:                              | 5V     | JP4*            | 5V               | JP8*            | 18:                                         | SCA    | A13¹              |
 +| 19:                              | HPD    | 1K to 5V        | NC               | 1K to 5V        | 19:                                         | 5V     | JP3               |
 +|  *jumper can disconnect Vdd                                                                  ||||| ¹shared with J1 I2C signals via jumper JP2                             |||
 +
 +EDK designs can use the xps_tft IP core (and its associated driver) to access the HDMI ports. The xps_tft core reads video data from the DDR2 memory, and sends it to the HDMI port for display on an external monitor.
 +
 +An EDK reference design available on the Digilent website (and included as a part of the User Demo) displays a gradient color bar on an HDMI-connected monitor. Another second EDK reference design inputs data from port J3 into onboard DDR2. Data is read from the DDR2 frame buffer and displayed on port J2. An xps_iic core is included to control the DDC on port J2 (this allows consumer devices to detect the Atlys).
 +
 +
 +
 +----
 +
 +
 +
 +====== Audio (AC-97) ======
 +
 +{{ :atlys:atlys:aud1.png?400|}}
 +
 +The Atlys board includes a National Semiconductor LM4550 AC ‘97 audio codec (IC3) with four 1/8” audio jacks for line-out (J5), headphone-out (J7), line-in (J4), and microphone-in (J6). Audio data at up to 18 bits and 48KHz sampling is supported, and the audio in (record) and audio out (playback) sampling rates can be different. The microphone jack is mono, all other jacks are stereo. The headphone jack is driven by the audio codec's internal 50mW amplifier. The table below summarizes the audio signals.
 +
 +The LM4550 audio codec is compliant to the AC ‘97 v2.1 (Intel) standard and is connected as a Primary Codec (ID1 = 0, ID0 = 0). The table below shows the AC ‘97 codec control and data signals. All signals are LVCMOS33.
 +
 +| __**Signal Name**__  | __**FPGA Pin**__  | __**Pin Function**__                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          |
 +| AUD-BIT-CLK          | L13               | 12.288MHZ serial clock output, driven at one-half the frequency of the 24.576MHz crystal input (XTL_IN).                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      |
 +| AUD-SDI              | T18               | Serial Data In (to the FPGA) from the codec. SDI data consists of AC ’97 Link Input frames that contain both configuration and PCM audio data. SDI data is driven on the rising edge of AUD-BIT-CLK.                                                                                                                                                                                                                                                                                                                                                                                                                                                          |
 +| AUD-SDO              | N16               | Serial Data Out (to the codec) from the FPGA. SDO data consists of AC ’97 Link Output frames that contain both configuration and DAC audio data. SDO is sampled by the LM4550 on the falling edge of AUD-BIT-CLK.                                                                                                                                                                                                                                                                                                                                                                                                                                             |
 +| AUD-SYNC             | U17               | AC Link frame marker and Warm Reset. SYNC (input to the codec) defines AC Link frame boundaries. Each frame lasts 256 periods of AUD-BIT-CLK. SYNC is normally a 48kHz positive pulse with a duty cycle of 6.25% (16/256). SYNC is sampled on the rising edge of AUD-BIT-CLK, and the codec takes the first positive sample of SYNC as defining the start of a new AC Link frame. If a subsequent SYNC pulse occurs within 255 AUD-BIT-CLK periods of the frame start it will be ignored. SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm Reset is used to clear a power- down state on the codec AC Link interface.  |
 +| AUD-RESET            | T17               | Cold Reset. This active low signal causes a hardware reset which returns the control registers and all internal circuits to their default conditions. RESET must be used to initialize the LM4550 after Power On when the supplies have stabilized. RESET also clears the codec from both ATE and Vendor test modes. In addition, while active, it switches the PC_BEEP mono input directly to both channels of the LINE_OUT stereo output.                                                                                                                                                                                                                   |
 +
 +The EDK reference design (available on the Digilent website) leverages our custom AC-97 pcore to accomplish several standard audio processing tasks such as recording and playing back audio data. 
 +
 +----
 +
 +====== Oscillators/Clocks ======
 +
 +The Atlys board includes a single 100MHz CMOS oscillator connected to pin L15 (L15 is a GCLK input in bank 1). The input clock can drive any or all of the four clock management tiles in the Spartan-6. Each tile includes two Digital Clock Managers (DCMs) and four Phase-Locked Loops (PLLs).
 +
 +DCMs provide the four phases of the input frequency (0º, 90º, 180º, and 270º), a divided clock that can be the input clock divided by any integer from 2 to 16 or 1.5, 2.5, 3.5... 7.5, and two antiphase clock outputs that can be multiplied by any integer from 2 to 32 and simultaneously divided by any integer from 1 to 32. 
 +
 +PLLs use VCOs that can be programmed to generate frequencies in the 400MHz to 1080MHz range by setting three sets of programmable dividers during FPAG configuration. VCO outputs have eight equally-spaced outputs (0º, 45º, 90º, 135º, 180º, 225º, 270º, and 315º) that can be divided by any integer between 1 and 128.
 +
 +----
 +
 +====== USB-UART Bridge (Serial Port) ======
 +
 +{{ :atlys:atlys:usb1.png?300|}}
 +
 +The Atlys includes an EXAR USB-UART bridge to allow PC applications to communicate with the board using a COM port. Free drivers allow COM-based (i.e., serial port) traffic on the PC to be seamlessly transferred to the Atlys board using the USB port at J17 marked UART. The EXAR part delivers the data to the Spartan-6 using a two-wire serial port with software flow control (XON/XOFF).
 +
 +Free Windows and Linux drivers can be downloaded from www.exar.com. Typing the EXAR part number “XR21V1410” into the search box will provide a link to the XR21V1410’s land page, where links for current drivers can be found. After the drivers are installed, I/O commands from the PC directed to the COM port will produce serial data traffic on the A16 and B16 FPGA pins.
 +
 +
 +----
 +
 +====== USB HID Host ======
 +
 +{{ :atlys:atlys:usb2.png?400|}}
 +
 +A Microchip PIC24FJ192 microcontroller provides the Atlys board with USB HID host capability. Firmware in the MCU microcontroller can drive a mouse or a keyboard attached to the type A USB connector at J13 labeled "Host". Hub support is not currently available, so only a single mouse or a single keyboard can be used. The PIC24 drives four signals into the FPGA – two are used as a keyboard port following the keyboard PS/2 protocol, and two are used as a mouse port following the mouse PS/2 protocol.
 +
 +Two PIC24 I/O pins are also connected to the FPGA’s two-wire serial programming port, so the FPGA can be programmed from a file stored on a USB memory stick. To program the FPGA, attach a memory stick containing a single .bit programming file in the root directory, load JP11, and cycle board power. This will cause the PIC processor to program the FPGA, and any incorrect bit files will automatically be rejected.
 +
 +{{ :atlys:atlys:usb3.png?300|}}
 +
 +To access the USB host controller, EDK designs can use the standard PS/2 core.  Reference designs posted on the Digilent website show an example for reading characters from a USB keyboard connected to the USB host interface. 
 +
 +Mice and keyboards that use the PS/2 protocol use a two-wire serial bus (clock and data) to communicate with a host device. Both use 11-bit words that include a start, stop, and odd parity bit, but the data packets are organized differently, and the keyboard interface allows bi-directional data transfers (so the host device can illuminate state LEDs on the keyboard). Bus timings are shown in the figure. The clock and data signals are only driven when data transfers occur, and otherwise they are held in the idle state at logic ‘1’. The timings define signal requirements for mouse-to-host communications and bi-directional keyboard communications. A PS/2 interface circuit can be implemented in the FPGA to create a keyboard or mouse interface.
 +
 +
 +----
 +
 +====== Keyboard ======
 +
 +The keyboard uses open-collector drivers so the keyboard, or an attached host device, can drive the two-wire bus (if the host device will not send data to the keyboard, then the host can use input-only ports).
 +
 +PS/2-style keyboards use scan codes to communicate key press data. Each key is assigned a code that is sent whenever the key is pressed. If the key is held down, the scan code will be sent repeatedly about once every 100ms. When a key is released, an F0 key-up code is sent, followed by the scan code of the released key. If a key can be shifted to produce a new character (like a capital letter), then a shift character is sent in addition to the scan code, and the host must determine which ASCII character to use. Some keys, called extended keys, send an E0 ahead of the scan code (and they may send more than one scan code). When an extended key is released, an E0 F0 key-up code is sent, followed by the scan code. Scan codes for most keys are shown in the figure. A host device can also send data to the keyboard. Below is a short list of some common commands a host might send.
 +
 +
 +| ED  | Set Num Lock, Caps Lock, and Scroll Lock LEDs. Keyboard returns FA after receiving ED, then host sends a byte to set LED status: bit 0 sets Scroll Lock, bit 1 sets Num Lock, and bit 2 sets Caps lock. Bits 3 to 7 are ignored.   |
 +| EE  | Echo (test). Keyboard returns EE after receiving EE.                                                                                                                                                                               |
 +| F3  | Set scan code repeat rate. Keyboard returns F3 on receiving FA, then host sends second byte to set the repeat rate.                                                                                                                |
 +| FE  | Resend. FE directs keyboard to re-send most recent scan code.                                                                                                                                                                      |
 +
 +
 +The keyboard can send data to the host only when both the data and clock lines are high (or idle). Since the host is the bus master, the keyboard must check to see whether the host is sending data before driving the bus. To facilitate this, the clock line is used as a “clear to send” signal. If the host pulls the clock line low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by 8-bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. The keyboard generates 11 clock transitions (at 20 to 30KHz) when the data is sent, and data is valid on the falling edge of the clock.
 +
 +Scan codes for most PS/2 keys are shown in the figure below.
 +
 +{{ :atlys:atlys:usb4.png?700 |}}