Xilinx’s Vivado Design Suite made its debut in 2012 as an integrated design environment for embedded development. More recently, the semiconductor company released its Vitis platform, which subsequently also includes Vivado, but also enables a broader range of new developers to design hardware. Seeing as how both of these offerings are for embedded development, both are from the same company, and heck, they both start with a “V”, we thought it would be helpful to spend a bit of time differentiating between the two tools.
What Do Vitis and Vivado Both Do?
We’ll get the big commonalities out of the way first – both Vitis and Vivado are used to create designs that run on FPGAs.
Speak the Right Language
Vivado is for creating hardware designs that run in an FPGA. These either consist of a set of hardware description language (HDL, typically Verilog or VHDL) files, or of a block design, which can include a variety of pre-built IP blocks (which at their core abstract away pre-written HDL). If a design includes a processor, Vitis will also be required to write the program to run on the processor, as Vivado only handles the programmable logic.
Vitis is for writing software to run in an FPGA, and is the combination of a couple of different Xilinx tools, including what was Xilinx SDK, Vivado High-Level Synthesis (HLS), and SDSoC. The functionality of each of these is now merged together under Vitis. To break each of these down:
- Xilinx SDK (Vitis): Write C/C++ to run on a processor in a design you created in Vivado. This code often ends up being at least partially used to configure and control elements of the hardware design – it’s easier to rebuild, tweak, and debug than the hardware portion is.
- Vivado HLS (Vitis HLS): Write C/C++ to be built into a block which you can include in a Vivado project. This block can often be reused in multiple projects, and even potentially be loaded up in Vivado for manual optimization.
- SDSoC (Vitis): Write C/C++ to be built into a block which the tool stitches into a previously created Vivado design. You take a platform with some I/O built in, and start accelerating certain data processing functions of your software design by building them into the hardware (while still writing them in software languages).
Different Processes for Different Folks
While the differences in languages are pretty cut and dry, the thought processes present more of a gray area. Both Vivado and Vitis can be used to create the highly-parallel hardware designs that run in FPGA fabric. Vitis also handles the part that runs sequentially in a processor. Parallel and sequential designs each have different snags that you can run into, though. For one, parallel hardware can introduce problems with one particularly slow part of a design effectively slowing down the entire design, even when that specific part is only very rarely used. In software, you would just have rare instances of the process running a bit slower, in hardware, you might have to run your clock slower than you’d like.
Notably, for debugging, when using pure hardware, you aren’t able to just run the design on the device and inspect any part of the design you’d like, as you are often able to with software. Debugging circuits (sometimes internal logic analyzers, sometimes an external logic analyzer) have to be specifically built into the hardware (the latter must be used through an external port), which can potentially slow it down. In addition, you still have to get all of that debug data out of the circuit and back to your PC, though hardware simulation (in Vivado or with other tools) helps with this.
Debugging through software on the other hand is more forgiving, as long as you build for debug. You can inspect any variable or memory address that exists without having to define what you want to look at before you build. Vitis also allows for simulation and emulation of hardware written in software languages as an added feature.
Both of Xilinx’s development environments have their uses, though Vitis is the one to use if you’re designing with both hardware and software. It’s also much more approachable for application programmers to configure hardware using code rather than having to dive into the heavier languages of VHDL or Verilog. You’ll be happy to know that the free web download of Vitis also includes Vivado as part of the toolchain, in the event you still want to use Vivado later for a more granular approach.
Here’s a link using the Genesys ZU with Vitis. Also, note that many of our projects in the Reference Center/Wiki have been migrated to Vitis. This is also relevant to the Basys 3, Nexys A7, Cmod A7, Arty S7, Arty Z7, Cora Z7, Arty A7, Nexys Video, Eclypse Z7, Zybo Z7, and Cmod S7. All can be found on our FPGA product page.