At some point during a FPGA engineers’ career, they will be faced with a difficult bug in their VHDL or Verilog code and they’ll ask themselves: “Why are we stuck with such difficult languages?” When we look to almost any other sort of chip, including CPUs and GPUs, a new, easy and well supported language emerges every other year. We have been stuck with Hardware Description Languages (HDLs) like Verilog and VHDL since the 80s. Why has no-one found a better method?
The history of VHDL
The answer to this is that the entire FPGA community is trying hard, but the nature of FPGAs makes this task difficult to pull off. To understand why this is, we need to look at the original purpose of FPGAs. The FPGA manufacturer Xilinx was founded in 1984, a full year after the release of VHDL. Originally, VHDL was designed by the US military as way of precisely documenting the behavior of Application Specific Integrated Circuits (ASICs).
Xilinx marketed FPGAs as way of emulating the behavior of ASICS without the need to manufacture them first. VHDL was then naturally supported by Xilinx’s tools because that is what ASIC engineers were using.
Verilog would also be invented in 1985 but kept as a proprietary language by Cadence Design Systems until 1990. It differed from VHDL because it was more similar to C++, but still simulated circuits. To this day, products like the Arty Z7 can still be programmed in these languages (https://digilent.com/shop/arty-a7-100t-artix-7-fpga-development-board/). They are now even supported by modern DevOps tools such as BeetleboxCI (http://beetlebox.org).
The difficulty to using HDL is because it is trying to map the behavior of a circuit at the Register Transfer Level (RTL). This is when data in the form of electronic signals moves from one register through a series of logical gate and to the next register within a certain period known as a clock cycle. A single ASIC will have billions of these signals moving at any given clock cycle and the designer uses VHDL to specify how this should occur. This naturally makes it language that only specialists can use and they then need a long time to properly simulate and debug FPGA designs.
Why are languages for other chips so much easier?
At a basic level, most other chips including CPUs, are designed to run a list of instructions sequentially. Typically, this will be tasks like moving data or perform arithmetic and this list of instructions would be written in the low-level assembly language.
This low-level language is difficult for humans to understand, so higher-level languages were invented that were more human readable like C. Even these languages though required programmers to understand concepts like memory management, so even higher-level languages were developed to make coding simpler.
High Level Synthesis (HLS) tools
If we could take these high-level languages, such as C, and use them for FPGA designs then we could gain the performance benefits of custom hardware without needing to write HDL. This is exactly what High Level Synthesis (HLS) tools have been attempting to do since the 90s. HLS tools have significantly improved since then and are supported by industry. Industrial tools include AMD’s (formerly Xilinx) Vivado HLS, Intel HLS Compiler and MicroChip’s SmartHLS.
These HLS compilers are often not perfect because these languages were designed to become list of instructions, not circuits. Only a limited amount of C can effectively be transformed into a circuit and still have the superior performance FPGAs are known for. Long sequences of ‘if’ statements perform poorly, whilst ‘for’ loops can be transformed well.
Because of this, new generation of tools have been created that use a combination of both CPUs and FPGAs. This combination can place the two on a single chip known as a System-on-Chip with a shared memory space. They can also be separate chips that are linked via a PCI interface. Tools that use this technique include Intel’s OneAPI and AMD’s Vitis Unified Development environment.
Domain Specific Tools
Another promising area are domain specific tools that build designs for specific applications. The most popular type of these tools is for the machine learning domain, which FPGA technology has shown a lot of promise in. TYpically these tools will take a model from a popular machine learning framework such as PyTorch or TensorFlow and then build an optimized design for that model.
This means that software developers can use FPGAS with no expertise, whilst also maintaining impressive performance. Community tools for this include FINN (https://github.com/Xilinx/finn) and HLS4ML (https://github.com/fastmachinelearning/hls4ml). Industrial tools include Vitis AI (https://www.xilinx.com/products/design-tools/vitis/vitis-ai.html), Intel OpenVINO (https://docs.openvino.ai/latest/home.html).
Finally, there have been attempts to make HDL more accessible by using languages software engineers are more familiar with. These differ from HLS tools because they enable developers to describe the hardware at the RTL level and not just improve performance of software concepts like ‘for’ loops. These attempts are mostly open source and run by the community. These include:
- Chisel (Scala) (https://www.chisel-lang.org/)
- SpinalHDL (Scala) (https://github.com/SpinalHDL/SpinalHDL)
- Amaranth HDL (Python) (https://github.com/amaranth-lang/amaranth)
- PyMTL (Python) (https://github.com/pymtl/pymtl3)
- PyRTL (Python) (https://github.com/UCSBarchlab/PyRTL)
- MyHDL (Python) (https://www.myhdl.org/)
The major problem with these languages is that the FPGA community is quite small, which makes supporting Open-Source projects more difficult than in software communities. There has also been little interest in industry tools supporting these HDLs and so most of these languages translate to an intermediate representation, such as an HLS tool, VHDL or Verilog.
Throughout most of the FPGA industry’s history, we have seen attempts to make better languages to develop with than Verilog or VHDL. From community driven efforts to produce HDLs in more friendly software languages to HLS tools that attempt to translate normal software code into high performing hardware. Most successfully, we have seen the rise of domain specific tools that can create optimized FPGA designs for specific applications like machine learning.
These new tools and languages do make FPGA technology better as they can provide FPGA-level performance with much less development effort. Unfortunately, they are only able to do so in limited circumstances. VHDL’s and Verilog’s fundamental ability to represent circuits at the RTL level as well as widespread industrial support means that there is still a solid future for these languages. The best we can do as engineers is learn these HDLs, but also be open and willing to learn and contribute to these new tools. Doing so can help improve productivity and expand the FPGA community,
Andrew Swirski is the Founder and Managing Director of Beetlebox, a powerful DevOps software designed specifically for IoT, embedded, and hardware projects.
2 Comments on “Can We Do Better Than Verilog and VHDL for FPGAs?”
Why bother writing a lengthy article when everyone knows that answer is that no… we can’t do better than VHDL and Verilog.
I think MyHDL is stalled.
Also of interest:
* Hardcaml: https://github.com/janestreet/hardcaml
* Clash: https://clash-lang.org/