Success Story: Verifying a New C++-to-RTL Solution

Earlier this year, we learned that VAXEL-EZ was deployed to help a team of engineers who had been developing a powerful new tool that converts C++ models to register-transfer level (RTL).

Although they were able to verify the output RTL up to the “simulation level,” they needed to test it on real hardware, a FPGA board, to make certain that the output RTL is actually “synthesizable.” Then, they faced multiple challenges as no member of the team had FPGA expertise or experience.

They had numerous questions:

  • Where do they find peripheral IP blocks that must be integrated with the DUT for verification?
  • How do they handle data I/O? How do they prepare memory controllers and datapaths?
  • How do they operate the FPGA to conduct the verification process? How do they run even the simplest operations such as start and stop, not to mention how to extract the verification results from the FPGA board?
  • To begin, how do they synthesize the RTL and how do they know if the RTL code is synthesizable?

And, of course, they had to find answers to all of the above within the limited timeframe and budget.

That was when the team found Digilent and VAXEL-EZ.

The Eclypse Z7 board was affordable and ready to use with a Xilinx Zynq chip. The VAXEL-EZ solution had all the features that enabled non-FPGA engineers to operate FPGA boards intuitively, and it even came with a set of prequalified IP blocks for verification (VIPs). The combination was perfect for the team and the decision to deploy the package was very quick.

As expected, the verification process went smoothly and their questions were answered within the given timeframe and budget. Setting up the Eclypse Z7 and the VAXEL EZ solution was simple and quick using a standard USB to connect a Windows PC and the FPGA board.

The DUT (in this case – a CNN block) was prepared as a black box and the peripheral blocks and the data i/o blocks were chosen from VAXEL’s prequalified VIP library. The FPGA Synthesis was pretty much automatic using the tool’s simple scripting tools (again, no member had previous experience with FPGA). The team just had to be careful about the total chip size.

VAXEL-EZ Hostware on a Windows PC provided a full range of menus to control/administer the FPGA board and the CNN hardware. VAXEL EZ Coreware, which runs on one of the ARM processors onboard the FPGA, helped when interactive operations were needed. Sending input data, collecting the test results – everything was very easy and the team was able to jump onto the actual verification tasks, skipping most of the raw-level preparation work for the FPGA board. This was the biggest benefit presented by the Digilent/VAXEL EZ combination. The team was able to genuinely focus on the most important problem on their hands – how they could make their new C++ to RTL tool produce truly synthesizable RTL code. By easily and quickly running the verification steps over and over on the real FPGA board, they were able to discover and eliminate all the problems and finish the C++ to RTL conversion tool.

If you’re interest in getting the VAXEL-EZ solution bundled with the Eclypse Z7, we’ve got you covered!

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