Using a CPU Clock for Clean Bus Captures with Digital Discovery: From the Forum

A Digilent forum user working on a vintage computing project needed to troubleshoot hardware built around a 6502 CPU. Their goal was to extract the CPU’s address and data bus activity using a Digital Discovery logic analyzer and export that activity as easy‑to‑read hexadecimal values.

While the signals displayed correctly in WaveForms, capturing data at a high internal sample rate quickly became unmanageable. Large acquisitions caused WaveForms to slow down or freeze – particularly in the Events tab – and the resulting data sets were far too large to meaningfully analyze or export.

What the user really wanted was simpler: capture one meaningful snapshot per CPU clock cycle.

The Challenge

Sampling the bus using the Digital Discovery’s internal clock resulted in:

• An extremely large number of samples captured at a high rate
• Increased memory usage inside WaveForms
• Long, repetitive logs where bus values were repeated for hundreds of samples

This made it difficult (or impossible) to identify individual bus transactions or export clean, human‑readable data.

The Answer: Use the CPU Clock as the Sample Clock

Instead of sampling continuously at a high internal rate, the Logic Analyzer can be configured to sample synchronously using an external signal, in this case, the CPU’s own clock.

By telling the Digital Discovery to sample only on each rising or falling edge of the CPU clock, the capture is reduced to exactly one sample per clock cycle.

This approach:

• Dramatically reduces the total number of samples
• Minimizes memory usage in WaveForms
• Produces bus captures that align cleanly with CPU operation

Rather than recording a dense stream of redundant data, the logic analyzer now records only when the CPU updates its address and data buses.

How to Set It Up in WaveForms

1. Connect Your Signals

   • Connect the address bus, data bus, and control signals (RW, RESET, etc.) to the Digital Discovery’s logic inputs
   • Connect the CPU clock to its own dedicated logic input pin

2. Configure the Logic Analyzer

   • Open the Logic Analyzer instrument
   • Click the gear icon on the right side of the control panel
   • Under Sampling, change the source from Internal to the pin connected to the CPU clock (for example, DIN0)
   • Select the appropriate edge (rising or falling), based on when your CPU’s bus data is valid
   • Set the Rate to at least 2× the CPU clock frequency so the Digital Discovery can reliably detect each edge

3. Reduce the Sample Count

   • Since you’re now sampling only on clock edges, you can significantly lower the total sample count while still capturing meaningful activity

Cleaning Up the View

To make the captured data easier to read in WaveForms:

• Open the plot gear icon at the top of the Logic Analyzer
• Under Global Options, change Vertical from the default triangular display to Logic Edges

This presents clean, vertical transitions and makes address and data changes much easier to follow.

Exporting the Data

Once captured, exporting the data is straightforward:

• Go to File → Export → Logic Analyzer Data
• Select only the signals you want to include
• Choose a hexadecimal format for address and data lines
• Export to CSV

The result is a compact, readable log of CPU activity, exactly what’s needed for tracing bus behavior during debugging.

Takeaway

Using an external clock for synchronous sampling turns the Digital Discovery into a powerful tool for CPU and bus analysis. By sampling only on meaningful clock edges, you avoid excessive data, reduce memory usage, and gain clear insight into system behavior, one clock cycle at a time.

This same technique can be applied to microcontrollers, FPGAs, and other clocked digital systems where clarity matters more than raw sample rate.

View the full forum thread HERE.