Atlys
programming and data transfer
line-out, mic, and headphone
connectors
connector
(XC6SLX45-CSG324C)
Note
The Atlys is retired and no longer for sale. Digilent support for this product will be limited.
The Atlys circuit board is a complete, ready-to-use digital circuit development platform based on a Xilinx Spartan-6 LX45 FPGA, speed grade -3. The large FPGA and on-board collection of high-end peripherals including Gbit Ethernet, HDMI Video, 128MByte 16-bit DDR2 memory, and USB and audio ports make the Atlys board an ideal host for a wide range of digital systems, including embedded processor designs based on Xilinx’s MicroBlaze. Atlys is compatible with all Xilinx CAD tools, including ChipScope, EDK, and the free ISE WebPack™, so designs can be completed at no extra cost.
The Spartan-6 LX45 is optimized for high-performance logic and offers:
- 6,822 slices, each containing four 6-input LUTs and eight flip-flops
- 2.1Mbits of fast block RAM
- four clock tiles (eight DCMs & four PLLs)
- six phase-locked loops
- 58 DSP slices
- 500MHz+ clock speeds
The Atlys board includes Digilent's newest Adept USB2 system, which offers device programming, real-time power supply monitoring, automated board tests, virtual I/O, and simplified user-data transfer facilities.
Tutorials
Example Projects
- Atlys Demo/BIST Config – ZIP
- Source code for Atlys Demo/BIST configuration (factory loaded into SPI Flash)
- Flash Memory Config – ZIP
- Source code for Atlys DDR2 and SPI Flash memory controller configuration
- VmodTFT Demo – ZIP
- This demo project is for the VmodTFT and either the Nexys3 or the Atlys. It continuously samples the VmodTFT's touch panel for X, Y and pressure values and lights up the pixels touched.
- EDK Microblaze Demo – Download
- This zip file contains an EDK demo project that illustrates how to use the AC97 codec on the Atlys board with Microblaze.
- EDK HDMI Demo – ZIP
- This zip file contains an EDK demo project that demonstrates using HDMI on the Atlys board. It accepts an HDMI input, buffers the input frames into memory, and then outputs the buffer to another HDMI port. This is implemented using PLB bus.
- ISE Demo – ZIP
- Download This zip file contains an ISE demo project that demonstrates the use of general I/O and UART on the Atlys board in VHDL.
- EDK Web Server – ZIP
- This zip file contains an EDK demo project that illustrates how to host a web server on the Atlys. It was built using EDK 14.3.
Additional Resources
Firmware
- Binary Image for BIST – ZIP
- Built binary image for Atlys_Demo_BIST. This can be used to restore the original factory image in the Atlys SPI Flash. To reprogram, use the Flash tab in the Adept Application.