System Settings

 
Environment Settings
Environment Variable xst ngdbuild map par
PATHEXT .COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC
< data not available > < data not available > < data not available >
Path M:\Xilinx\12.2\ISE_DS\ISE\\lib\nt;
M:\Xilinx\12.2\ISE_DS\ISE\\bin\nt;
M:\Xilinx\12.2\ISE_DS\PlanAhead\bin;
M:\Xilinx\12.2\ISE_DS\ISE\bin\nt;
M:\Xilinx\12.2\ISE_DS\ISE\lib\nt;
M:\Xilinx\12.2\ISE_DS\EDK\bin\nt;
M:\Xilinx\12.2\ISE_DS\EDK\lib\nt;
M:\Xilinx\12.2\ISE_DS\common\bin\nt;
M:\Xilinx\12.2\ISE_DS\common\lib\nt;
C:\Program Files\Common Files\ArcSoft\Bin;
C:\Program Files\Common Files\Microsoft Shared\Windows Live;
C:\WinAVR-20100110\bin;
C:\WinAVR-20100110\utils\bin;
C:\Program Files\PC Connectivity Solution\;
M:\Xilinx\11.1\ChipScope\bin\nt;
M:\Xilinx\11.1\common\bin\nt;
M:\Xilinx\11.1\common\lib\nt;
M:\Xilinx\11.1\EDK\bin\nt;
M:\Xilinx\11.1\EDK\lib\nt;
M:\Xilinx\11.1\PlanAhead\bin;
M:\Xilinx\11.1\ISE\bin\nt;
M:\Xilinx\11.1\ISE\lib\nt;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\Intel\DMIX;
C:\Program Files\Dell\DW WLAN Card;
C:\Program Files\NTRU Cryptosystems\NTRU TCG Software Stack\bin\;
C:\Program Files\Wave Systems Corp\Gemalto\Access Client\v5\;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files\Microchip\MPLAB C32 Suite\bin;
C:\Program Files\Microchip\MPLAB IDE\VDI
< data not available > < data not available > < data not available >
XILINX M:\Xilinx\12.2\ISE_DS\ISE\ < data not available > < data not available > < data not available >
XILINX_DSP M:\Xilinx\12.2\ISE_DS\ISE < data not available > < data not available > < data not available >
XILINX_EDK M:\Xilinx\12.2\ISE_DS\EDK < data not available > < data not available > < data not available >
XILINX_PLANAHEAD M:\Xilinx\12.2\ISE_DS\PlanAhead < data not available > < data not available > < data not available >
 
Synthesis Property Settings
Switch Name Property Name Value Default Value
-ifn   signal_tester.prj  
-ifmt   mixed Mixed
-ofn   signal_tester  
-ofmt   NGC NGC
-p   xc6slx45-2-csg324  
-top   signal_tester  
-opt_mode Optimization Goal Speed Speed
-opt_level Optimization Effort 1 1
-power Power Reduction NO No
-iuc Use synthesis Constraints File NO No
-keep_hierarchy Keep Hierarchy No No
-netlist_hierarchy Netlist Hierarchy As_Optimized As_Optimized
-rtlview Generate RTL Schematic Yes No
-glob_opt Global Optimization Goal AllClockNets AllClockNets
-read_cores Read Cores YES Yes
-write_timing_constraints Write Timing Constraints NO No
-cross_clock_analysis Cross Clock Analysis NO No
-bus_delimiter Bus Delimiter <> <>
-slice_utilization_ratio Slice Utilization Ratio 100 100
-bram_utilization_ratio BRAM Utilization Ratio 100 100
-dsp_utilization_ratio DSP Utilization Ratio 100 100
-reduce_control_sets   Auto Auto
-fsm_extract   YES Yes
-fsm_encoding   Auto Auto
-safe_implementation   No No
-fsm_style   LUT LUT
-ram_extract   Yes Yes
-ram_style   Auto Auto
-rom_extract   Yes Yes
-shreg_extract   YES Yes
-rom_style   Auto Auto
-auto_bram_packing   NO No
-resource_sharing   YES Yes
-async_to_sync   NO No
-use_dsp48   Auto Auto
-iobuf   YES Yes
-max_fanout   100000 100000
-bufg   16 16
-register_duplication   YES Yes
-register_balancing   No No
-optimize_primitives   NO No
-use_clock_enable   Auto Auto
-use_sync_set   Auto Auto
-use_sync_reset   Auto Auto
-iob   Auto Auto
-equivalent_register_removal   YES Yes
-slice_utilization_ratio_maxmargin   5 0
 
Operating System Information
Operating System Information xst ngdbuild map par
CPU Architecture/Speed Intel(R) Core(TM)2 Duo CPU T9600 @ 2.80GHz/2793 MHz <  data not available  > <  data not available  > <  data not available  >
Host albertf-PC <  data not available  > <  data not available  > <  data not available  >
OS Name Microsoft <  data not available  > <  data not available  > <  data not available  >
OS Release major release (build 7600) <  data not available  > <  data not available  > <  data not available  >