d_usb_epp_dstm Project Status (09/08/2010 - 11:05:07) | |||
Project File: | d_usb_epp_dstm.xise | Parser Errors: | No Errors |
Module Name: | d_usb_epp_dstm | Implementation State: | Synthesized |
Target Device: | xc6slx45-2csg324 |
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No Errors |
Product Version: | ISE 12.2 |
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194 Warnings (0 new) |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice Registers | 542 | 54576 | 0% | |
Number of Slice LUTs | 1011 | 27288 | 3% | |
Number of fully used LUT-FF pairs | 434 | 1119 | 38% | |
Number of bonded IOBs | 0 | 218 | 0% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Wed Sep 8 11:05:07 2010 | 0 | 194 Warnings (0 new) | 12 Infos (0 new) | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |