signal_tester Project Status (08/11/2010 - 13:28:54)
Project File: signal_tester.xise Parser Errors: No Errors
Module Name: signal_tester Implementation State: Synthesized
Target Device: xc6slx45-2csg324
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
178 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 1003 54576 1%
Number of Slice LUTs 1452 27288 5%
Number of fully used LUT-FF pairs 813 1642 49%
Number of bonded IOBs 247 218 113%
Number of BUFG/BUFGCTRLs 2 16 12%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Aug 11 13:32:51 20100178 Warnings (0 new)10 Infos (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/11/2010 - 13:33:01