d_usb_epp_dstm Project Status (09/08/2010 - 11:05:07)
Project File: d_usb_epp_dstm.xise Parser Errors: No Errors
Module Name: d_usb_epp_dstm Implementation State: Synthesized
Target Device: xc6slx45-2csg324
  • Errors:
No Errors
Product Version:ISE 12.2
  • Warnings:
194 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 542 54576 0%
Number of Slice LUTs 1011 27288 3%
Number of fully used LUT-FF pairs 434 1119 38%
Number of bonded IOBs 0 218 0%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentWed Sep 8 11:05:07 20100194 Warnings (0 new)12 Infos (0 new)
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 09/08/2010 - 11:05:07