The Digilent Pmod CAN (Revision B) is a CAN 2.0B controller with an integrated transceiver. The embedded Microchip MCP25625 chip connects directly to the physical CAN bus and meets automotive requirements for high-speed (1 Mb/s), low quiescent current, electromagnetic compatibility, and electrostatic discharge.
Parameter | Min | Typical | Max | Units |
---|---|---|---|---|
Power Supply Voltage (Vcc) | 2.7 | 5.5 | V | |
High-Level Input Voltage (RxCAN) | 2 | - | Vcc+1 | V |
Low-Level Input Voltage (RxCAN) | -0.3 | - | 0.15*Vcc | V |
High-Level Output Voltage (TxCAN) | Vcc-0.7 | - | - | V |
Low-Level Output Voltage (TxCAN) | - | - | 0.6 | V |
Bit Frequency | 14.4 | - | 1000 | kHz |
Transmitter | Min | Typ | Max | Units |
Recessive Bus Output Voltage (CANH & CANL) | 2.0 | 0.5 Vcc | 3.0 | V |
Dominant Output Voltage (CANH) | 2.75 | 3.50 | 4.50 | V |
Dominant Output Voltage (CANL) | 0.50 | 1.50 | 2.25 | V |
Dominant Differential Output Voltage | 1.5 | 2.0 | 3.0 | V |
Receiver | Min | Typ | Max | Units |
Recessive Differential Input Voltage (normal mode) | -1.0 | - | +0.5 | V |
Dominant Differential Input Voltage (normal mode) | 0.9 | - | Vcc | |
Parameter | Value | Units | ||
Standby Current | 10 | μA |
Header J2 | Header J1 | Header J3 | ||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Pin | Signal | Description | Pin | Signal | Description | Pin | Signal | Description | Pin | Signal | Description | Pin | Signal | Description |
1 | CS | Chip Select | 7 | INT | Interrupt | 1 | N/C | Not Connected | 7 | CANH | CAN High-Level Voltage I/O | 1 | CANL | CAN Low-Level Voltage I/O |
2 | MOSI | Master-Out-Slave-In | 8 | RST | Reset | 2 | CANL | CAN Low-Level Voltage I/O | 8 | N/C | Not Connected | 2 | CANH | CAN High-Level Voltage I/O |
3 | MISO | Master-In-Slave-Out | 9 | Rx0BF | Receive Buffer 0 Full Interrupt | 3 | GND | Power Supply Ground | 9 | N/C | Not Connected | 3 | GND | Power Supply Ground |
4 | SCK | Serial Clock | 10 | Rx1BF | Receive Buffer 0 Full Interrupt | 4 | N/C | Not Connected | S1 | GND | Power Supply Ground | Jumpers | ||
5 | GND | Power Supply Ground | 11 | GND | Power Supply Ground | 5 | N/C | Not Connected | S2 | GND | Power Supply Ground | JP1 | Loaded/ Unloaded | End of bus terminated with a combined 120Ω impedance/ Do not terminate the end of the bus |
6 | VCC | Power Supply (3.3V) | 12 | VCC | Power Supply (3.3V) | 6 | GND | Power Supply Ground | JP2 | Loaded/ Unloaded | Terminate the CAN bus lines with a capacitor to ground/ No termination |
The pins on the pin header are spaced 100 mil apart. The PCB is 1.8 inches long on the sides parallel to the pins on the pin header and 1.4 inches long on the sides perpendicular to the pin header.
The Pmod CAN utilizes the Microchip MCP25625 to enable CAN communication with a variety of external devices. A complete CAN solution with a controller and transceiver can be implemented on a system board by communicating with the host board via the SPI protocol in SPI mode 0 or 3. The two differential lines on the transceiver, CANH and CANL, enable balanced differential signaling to eliminate most of the electromagnetic field (EMF) and provide high noise immunity within the system.
The Pmod CAN communicates with the host board via the SPI protocol. By driving and keeping the Chip Select line (pin 1) at a logic level low, users may communicate back and forth with the Pmod depending on whether or not both sets of data lines are enabled. The embedded chip on the Pmod operates in SPI Mode 0 or 3, with data captured on the rising edge of the clock and data transferred on the falling edge of the clock, and a minimum clock cycle time of 100 nanoseconds as per Table 7-6 (page 70) of the Microchip MCP25625 datasheet.
Nine SPI instructions are available to read the status of the receiver, load a transmit buffer, modify bits in a register and more. Most of the instruction commands are single byte instructions followed by an address byte. More information is available in the Quick Start section as well as Section 5 (page 55) of the MCP25625 datasheet.
The CANINTE register (page 51) enables the generation of interrupts on Pin 7.
CANINTE 0x2B | ||||
---|---|---|---|---|
Bit Name | Bit Number | Bit Description | Bit Values | Functional Description |
MERRE | [7] | Message Error Interrupt Enable Bit | 0¹ | 1-Interrupt on error during message reception or transmission/0-Disabled |
WAKIE | [6] | Wake-up Interrupt Enable Bit | 0¹ | 1-Interrupt on CAN bus activity/0-Disabled |
ERRIE | [5] | Error Interrupt Enable Bit | 0¹ | 1-Interrupt on EFLG error condition change/0-Disabled |
TX2IE | [4] | Transmit Buffer 2 Empty Interrupt Enable Bit | 0¹ | 1-Interrupt on TXB2 becoming empty/0-Disabled |
TX1IE | [3] | Transmit Buffer 1 Empty Interrupt Enable Bit | 0¹ | 1-Interrupt on TXB1 becoming empty/0-Disabled |
TX0IE | [2] | Transmit Buffer 0 Empty Interrupt Enable Bit | 0¹ | 1-Interrupt on TXB0 becoming empty/0-Disabled |
RX1IE | [1] | Receive Buffer 1 Full Interrupt Enable Bit | 0¹ | 1-Interrupt when message received in RXB1/0-Disabled |
RX0IE | [0] | Receive Buffer 0 Full Interrupt Enable Bit | 0¹ | 1-Interrupt when message received in RXB0/0-Disabled |
¹ – This is the default value on power-up or reset
The CANINTF register (page 52) holds the flags of all the interrupts that are enabled through the CANINTE register. If an interrupt flag is set, it must be cleared by the system board to reset the interrupt condition.
CANINTF 0x2C | ||||
---|---|---|---|---|
Bit Name | Bit Number | Bit Description | Bit Values | Functional Description |
MERRF | [7] | Message Error Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
WAKIF | [6] | Wake-up Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
ERRIF | [5] | Error Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
TX2IF | [4] | Transmit Buffer 2 Empty Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
TX1IF | [3] | Transmit Buffer 1 Empty Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
TX0IF | [2] | Transmit Buffer 0 Empty Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
RX1IF | [1] | Receive Buffer 1 Full Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
RX0IF | [0] | Receive Buffer 0 Full Interrupt Flag Bit | 0¹ | 1-Interrupt pending/0-No interrupt pending |
¹ – This is the default value on power-up or reset
The CANSTAT register (page 54) provides the status of the CAN controller and the source of the interrupt flag.
CANSTAT 0xXE | ||||
---|---|---|---|---|
Bit Name | Bit Number | Bit Description | Bit Values | Functional Description |
OPMOD2 | [7] | Operation Mode Bit 2 | 1¹ | See the Operation Mode Bit Table |
OPMOD1 | [6] | Operation Mode Bit 1 | 0¹ | See the Operation Mode Bit Table |
OPMOD0 | [5] | Operation Mode Bit 0 | 0¹ | See the Operation Mode Bit Table |
– | [4] | Unimplemented | 0¹ | Unimplemented - read as '0' |
ICOD2 | [3] | Interrupt Flag Code Bit 2 | 0¹ | See the Interrupt Flag Code Bit Table |
ICOD1 | [2] | Interrupt Flag Code Bit 1 | 0¹ | See the Interrupt Flag Code Bit Table |
ICOD0 | [1] | Interrupt Flag Code Bit 0 | 0¹ | See the Interrupt Flag Code Bit Table |
– | [0] | Unimplemented | 0¹ | Unimplemented - read as '0' |
¹ − This is the default value on power-up or reset
Operation Mode Bit Table | |
---|---|
Bit values for Operation Mode bits 2,1,0 | Mode |
0,0,0 | Device is in Normal Operation Mode |
0,0,1 | Device is in Sleep Mode |
0,1,0 | Device is in Loopback Mode |
0,1,1 | Device is in Listen-Only Mode |
1,0,0 | Device is in Configuration Mode |
Interrupt Flag Table | |
---|---|
Bit values for Interrupt Flag bits 2,1,0 | Interrupt |
0,0,0 | No Interrupt |
0,0,1 | Error Interrupt |
0,1,0 | Wake-up Interrupt |
0,1,1 | TBX0 Interrupt |
1,0,0 | TBX1 Interrupt |
1,0,1 | TBX2 Interrupt |
1,1,0 | RBX0 Interrupt |
1,1,1 | RBX1 Interrupt |
Here is the series of SPI commands to set up, transmit, and receive data on the Pmod CAN:
The CAN protocol uses two communication lines, CANH and CANL, to enable communication between multiple CAN transceivers called nodes. The two bus lines are actively driven to produce a differential voltage greater than 1.5 V, resulting in the Dominant transmission state. CAN transceivers will interpret a dominant transmission as a logic low state. A logic high state is created by neither bus driving their lines so that they idle at approximately the same voltage, typically Vcc/2 as biased by the common mode transceiver. This state is a Recessive transmission and typically has a differential voltage of less than ±100 mV.
Similar to UART, all nodes on a CAN network must operate at the same nominal bit rate as data is transmitted without a clock signal in an asynchronous format. The Pmod CAN is compliant with CAN 2.0B (ISO-11898-2 and ISO-11898-5). In addition to the de-facto RS-232 header, Header J1, screw terminals are provided on Header J3 for other CAN devices that use twisted pair wiring.
Timing diagrams from page 58 of the MCP25625 datasheet for the Pmod CAN for data coming in and out through SPI are provided below. The timing values for the parameters shown in the images can be found in Table 7-6 (page 70) of the MCP25625 datasheet.
The schematics of the Pmod CAN are available here. Additional information about the CAN controller and transceiver including communication modes and specific timings of the chip can be found in the datasheet here.
Example code demonstrating how to get information from the Pmod CAN can be found on its Resource Center here.
If you have any questions or comments about the Pmod CAN, feel free to post them under the appropriate section (“Add-on Boards”) of the Digilent Forum.