Zmod SDR Reference Manual

The Digilent Zmod SDR is a digitizer designed for software-defined radio and RF applications. It is a SYZYGY™ ¹⁾-compatible pod containing a dual-channel ADC and the associated front end. The Zmod SDR is intended to be used with any SYZYGY™ compatible carrier board. It features a wide input bandwidth, allowing for undersampling applications - capturing signals with frequencies much higher than the baseline 122.88 MS/s sample rate's associated Nyquist frequency. An on-board low-jitter clock generator and low-noise design provide the precision necessary to capture fast radio signals. When paired with an Eclypse Z7 host board, the Zmod is supported in GNU Radio, providing a convenient and familiar interface for SDR experts and researchers.

This document describes the Zmod SDR's circuits, with the intent of providing a better understanding of its electrical functions, operations, and a more detailed description of the hardware’s features and limitations. It is not intended to provide enough information to enable complete duplication of the Zmod SDR, but can help users to design custom configurations for programmable parts in the design.

Zmod SDR's block diagram is presented in Fig. 1 below. The core of the Analog Zmod SDR is a dual channel, high speed, low power ADC, as shown in Table 1. The carrier board is responsible to configure the internal registers of the ADC and clock generator circuits, and receive the data.

The Front End signals use the “SC” index. Signals and equations also use certain naming conventions. Analog voltages are prefixed with a “V” (for voltage), and suffixes and indexes are used in various ways: to specify the location in the signal path (IN, BUF, ADC, etc.); to indicate the related instrument (SC, etc.); to indicate the channel (1 or 2); and to indicate the type of signal (P, N, or diff). Referring to the block diagram in Fig. 1 below:

• The Analog Input instrument block includes:
  • Front End: AC coupling, differential balance, impedance matching, and protection circuitry
  • ADC Reference: generates and buffers reference voltages for the ADC
  • Clock Generator: generates a low jitter, programmable frequency clock for data acquisition
  • ADC: the analog-to-digital converter for both input channels
• The Power Supplies and Control block generates all internal supply voltages
• The MCU works as an I2C memory for the DNA: the standard SYZYGY™ pod identification information

In the sections that follow, schematics are not shown separately for identical blocks. For example, the Front End schematic is only shown for channel 1 since the schematic for channel 2 is identical. Indexes are omitted where not relevant. As an example, in equation \ref{1} below, $V_{SCOPE-SMA}$ does not contain the channel index (because the equation applies to both channels 1 and 2).

Fig. 2 shows the analog input frontend stage.

• C₂ provides controlled capacitance, much higher than the parasitical capacitance of subsequent stages
• C₁, C₃ realize AC coupling
• T₁ balun balances the single ended input to differential
• T₂ transformer doubles the voltage
• R₁, R₃, D₁, D₂ clamp the ADC differential input voltage to ±1.2 V
• R₂ connects the ADC Common Mode Voltage to the midpoint of the transformer secondary winding, filtered and decoupled by C₄ and C₅
• R₄₄ in figure Fig. 3 reflects through the T2 transformer as a 50 Ω Input Impedance of the Front End

The input divider provides:

• Analog input impedance = 50 Ω || 5 pF
• A gain of 2
• Balanced differential input to the ADC
• Flat gain over a large frequency range

The maximum voltage rating for analog inputs is limited to:

$$-0.5V<V_{SCOPE1-SMA}<0.5V\label{1}\tag{1}$$

The DC gain is: $$\frac {V_{ADC-SC2}}{V_{SCOPE1-SMA}}=2\label{2}\tag{2}$$

The nominal input voltage range is: $$-0.5V \le V_{SCOPE1-SMA} \le 0.5V \label{3}\tag{3}$$

The input impedance at 1 MHz is:

$$Z_{in} = \frac{R_{44}}{4} = 50 Ω\label{4}\tag{4}$$

Experiments shown that there is significant parasitic capacity in the input node: C_P includes the capacity to GND of the layout, balun, transformer, diodes.

The equivalent capacitance of the input divider (SCOPE1_SMA node) is:

$$C_{in} = C_{2} || C_{P} = 5pF\label{6}\tag{6}$$

The ADC uses the internal 1 V reference voltage which is filtered and decoupled by C₆₉ and C₇₀ in Fig. 3.

The Zmod SDR uses a dual channel, high speed, low power, 14-bit, 125 MS/s ADC, as shown in Fig. 4.

The differential clock is AC-coupled and the line is impedance matched. The ADC generates the common mode reference voltage (VCM_SC) to be used in the buffer stage.

The digital stage of the ADC and the corresponding FPGA bank are supplied at 1.8 V by the SYZYGY™ voltage V_adj.

The multiplexed mode is used, to combine the two channels on a single data bus and minimize the number of used FPGA pins. CLKOUT_SC is provided to the FPGA for synchronizing data.

IC1 in the figure below is a low-jitter clock generator: CDCE6214. It has a PLL loop, with divider and multiplier registers, for programmable output frequencies. An input MUX can select between two possible clock sources:

• Zmod SDR uses a crystal for a low-jitter clock source at CLKIN_XTAL pins
• As an alternative, the SYZYGY C2P clock can be selected at CLKIN_PLL pins, for a flexible, lower-quality clock source, originating at the carrier board FPGA

OUT4 pins generate the LVDS clock for the ADC, CLKIN_ADC.

The circuit is programmed via a dedicated I2C bus, which is not the standard SYZYGY I2C bus used to communicate with the ADN MCU of the Zmod.

Fig. 5 and Fig. 6 show the time and spectral images of a single-tone signal.

The Signal is a clean 1 V amplitude, 10 MHz sinus signal, generated with a Agilent 33500B Waveform Generator.

It is acquired with a Zmod SDR on a Eclypse Z7 system board using WaveForms. The sampling clock is generated by the IC1 in Fig. 4. The source clock is the XTAL for Fig. 5, respectively CLKIN_PLL (from the FPGA) for Fig. 6.

The nominal differential ADC input voltage range is:

$$-1V<V_{ADC\;diff}<1V\label{8}\tag{8}$$

The total analog gain (from the SMA connectors to the ADC inputs) is:

$$Analog\; gain = \frac{V_{ADC\;diff}}{V_{SCOPE-SMA}}=2\label{9}\tag{9}$$

The Zmod SDR input voltage range is:

$$ -0.5V<V_{SCOPE-SMA}<0.5V=Range\label{10}\tag{10}$$

With the 14-bit ADC, the absolute resolution:

$$ R_{abs} = \frac{1V}{2^{n}}=61μV\label{11}\tag{11}$$

For V_in voltage value at the input of the analog channel, the Zmod SDR sends a signed n-bit integer, N. This value is used to compute V_in:

$$V_{SCOPE-SMA} = \frac{N \cdot Range }{2^{n-1}} \label{12}\tag{12}$$

Where:

• n = 14, the number of bits of the ADC
• V_in= the corrected value of the input voltage
• N = the n bit, 2's complement integer number returned by the ADC
• Range = 0.5 V = the ideal Range of the input stage

Keep in mind that the Zmod SDR input impedance is 50 Ω. If the input signal generator (antenna) has a non-zero output impedance, the input voltage is divided from the theoretical input voltage:

$$V_{SCOPE-SMA} = V_{in}\frac{Z_{in}}{Z_{in}+Z_{out}} \label{13}\tag{13}$$

The Zmod SDR is designed for an equivalent input impedance of 50 Ω: $$Z_{in} = \frac{R_{43}}{2^{n-1}} \label{14}\tag{14}$$

Where:

• R43 = 200 Ω,
• V_in = 4 = T2 impedance ratio

However, the parasitic effects and component non-idealities make the input impedance a function of frequency, as shown in Fig. 7. A PXIe-5832 VNA is used to measure the Resistance and Reactance. Impedance and Phase are computed in a spreadsheet.

The VNA settings are:

• Display Impedance
• 5 dBm (1 V amplitude)
• Frequency range 0.5…479.5 MHz - first Nyquist zone
• 480 steps
• Step size 1 MHz
• 100 ms delay

Fig. 8 shows a typical spectral characteristic of the Zmod SDR. A PXIe-5832 VNA is used to generate the input sinus signal of 5 dBm (1 V amplitude with infinite impedance load). The tested Zmod SDR is mounted on a Eclypse Z7 board. The WaveForms software runs a Network Analyzer instrument. The Network Analyzer settings are:

• Sampling Clock Frequency FSample = 120 MHz
• External input
• 500 kHz to 59.5 MHz (first Nyquist zone)
• 60 steps
• 10 ms settling time

The VNA settings are:

• 5 dBm (1 V amplitude)
• 100 ms delay
• 60 steps
• Step size 1 MHz
• Each reference was recorded with VNA set to cover one Nyquist zone in 60 steps:
  • Ref1: 0.5…59.5 MHz - first Nyquist zone
  • Ref2: 60.5…119.5 MHz - second Nyquist zone, mirrored
  • Ref3: 120.5…179.5 MHz - third Nyquist zone, shifted
  • Ref4: 180.5…239.5 MHz - fourth Nyquist zone, mirrored
  • Ref5: 240.5…299.5 MHz - fifth Nyquist zone, shifted
  • Ref6: 300.5…359.5 MHz - sixth Nyquist zone, mirrored
  • Ref7: 360.5…419.5 MHz - seventh Nyquist zone, shifted
  • Ref8: 420.5…479.5 MHz - eight Nyquist zone, mirrored

The first Nyquist zone is visible as direct transfer characteristic. The next Nyquist zones are visible as mirror/shifted frequency images in the first Nyquist range.

Fig. 9 shows the “unfolded” spectral characteristic of the Zmod SDR. The References from Fig. 5 are shifted back and unmirrored to show the continuous frequency characteristic over the full range of 500Hz to 479.5MHz.

Fig. 10 shows the low-frequency spectral characteristic (5kHz to 500kHz) of the Zmod SDR, which is AC-coupled. A Zmod AWG and the tested Zmod SDR are mounted on an Eclypse Z7 board. The WaveForms software runs a Network Analyzer instrument. The Network Analyzer settings are:

• Input: Zmod AWG1411, 1V amplitude, 5 kHz to 1 MHz, 200 steps
• WaveForms on Eclypse Z7, sampling at 120 MS/s
• Network Analyzer set for Wavegen1 input
• 5 kHz to 1 MHz (AC coupling char)
• Ref1: Ch1
• Ref2: Ch2

The ATtiny44 MCU in Fig. 11 works as an I2C memory, storing the SYZYGY™ DNA information and the Calibration Coefficients. The J5 connector is used for programming the MCU and the SYZYGY™ DNA at manufacturing.

The DNA and the Factory Calibration Coefficients are stored in the Flash memory of the MCU, which appears to the I2C interface as “read-only”. The User Calibration Coefficients are stored in the EEPROM memory of the MCU, which is write-protected via a magic number at a magic address. The memory structure can be consulted below. Since the amplitude accuracy is not important in SDR applications, there is no calibration process implemented at the Zmod SDR manufacturing, and no Calibration Coefficients are saved, neither in the Factory Calibration Coefficients nor in the User Calibration Coefficients fields, except for the manufacturing test date.

• Program Memory Type: Flash
• Program Memory Size (KB): 4
• CPU Speed (MIPS/DMIPS): 20
• SRAM Bytes: 256
• Data EEPROM/HEF (bytes): 256
• Digital Communication Peripherals: 1-SPI, 1-I2C
• Capture/Compare/PWM Peripherals: 1 Input Capture, 1 CCP, 4PWM
• Timers: 1 x 8-bit, 1 x 16-bit
• Number of Comparators: 1
• Temperature Range (C): -40 to 85
• Operating Voltage Range (V): 1.8 to 5.5
• Pin Count: 14
• Low Power: Yes

The Zmod SDR is compliant with SYZYGY™ Specification. It contains an MCU able to calculate the Geographical Address and provide the DNA information via I2C. The DNA is stored in the MCU FLASH at the address range: 0x8000 - 0x80FF with the following structure:

Since the amplitude accuracy is not important in SDR applications, there is no calibration process implemented at the Zmod SDR manufacturing, and no Calibration Coefficients are saved, nor in the Factory Calibration Coefficients neither in User Calibration Coefficients fields, except for the manufacturing test date. All Cx constants in the table below are 0x00. The structure of the calibration data is shown below:

At the power up the EEPROM memory is protected against write operations. To disable the write protection one has to write a magic number to a magic address over I2C. To re-enable the write protection one has to write any other number to the magic address.

This block includes the internal power supplies.

The Zmod Scope gets the digital rails from the carrier board, via the SYZYGY connector:

• VCC3V3 - used for the MCU and analog supplies
• Vadj = 1.8 V - used for the ADC digital rail

The internal analog rail sequence is:

• AVCC1V8 - ADC analog rail

The SYZYGY™ connector in provides the interface with the carrier board. The used signals are:

• Power rails
  • VCC5V0
  • VCC3V3
  • VADJ - needs to be set by the carrier board to 1.8 V
  • GND
  • Shield
• SYZYGY™ I2C bus:
  • MCU_SCLUSCK
  • MCU_SDA_MOSI
• ADC differential input clock
  • CLKIN_ADC_P
  • CLKIN_ADC_N
• ADC single-ended output clock:
  • CLKOUT_ADC (coupled with GND in the differential P2C pair)
• R_GA for geographical address identification
• SYNC_ADC for ADC internal clock divider synchronization
• ADC data bus: DOUT_ADC_0…13
• ADC SPI bus:
  • CS_SC1n
  • SCLK_SC
  • SDIO_SC
• Relay control
  • SCx_yy_z

Written by Mircea Dabacan, PhD, Technical University of Cluj-Napoca Romania