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Files in reference:programmable-logic:zedboard
- fpga_package_pin_to_fmc.pdf
- 2017/08/02 21:03
- 234.5 KB
- zedboard-0.png
- 600×473
- 2016/07/08 19:29
- 410.2 KB
- zedboard-1.png
- 600×625
- 2016/07/08 19:29
- 538.9 KB
- zedboard-2.png
- 600×535
- 2016/07/08 19:29
- 630.6 KB
- zedboard-3.png
- 600×532
- 2016/07/08 19:29
- 636.3 KB
- zedboard-4.png
- 600×648
- 2016/07/08 19:29
- 500.1 KB
- zedboard-5.png
- 600×496
- 2016/07/08 19:29
- 393.9 KB
- zedboard-schematic-rev-e1-public.pdf
- 2020/11/12 20:34
- 3.5 MB
- zedboarddd3_fixedplatform.png
- 799×711
- 2020/11/03 18:01
- 25 KB
- zedboardddr3_changeddr.png
- 971×748
- 2020/11/03 18:01
- 47.3 KB
- zedboardddr3_exportincludebitstream.png
- 457×239
- 2020/11/03 18:01
- 8 KB
- zedboardddr3_fbga_code.png
- 726×721
- 2020/11/03 01:18
- 840.3 KB
- zedboardddr3_generatebitstream.png
- 1254×852
- 2020/11/03 19:04
- 89.8 KB
- zedboardddr3_hw_handoff.png
- 799×711
- 2020/11/03 18:01
- 17.4 KB
- zedboardddr3_includebitstream.png
- 799×712
- 2020/11/03 18:01
- 17.3 KB
- zedboardddr3_openblockdesign.png
- 668×647
- 2020/11/03 19:24
- 33.9 KB
- zedboardddr3_recustomizeip.png
- 973×750
- 2020/11/03 18:01
- 26.7 KB
- zedboardddr3_sdk_hwplatformchange.png
- 462×122
- 2020/11/03 18:01
- 10.2 KB
- zedboardddr3_validatedesign.png
- 844×542
- 2020/11/03 19:04
- 35 KB
- zedboardddr3_vitis_hwpath.png
- 1090×297
- 2020/11/03 18:01
- 24.4 KB
- zedboardddr3_vitis_hwspecification.png
- 464×93
- 2020/11/03 18:01
- 15.4 KB
- zedboardddr3_zynqip_blockdiagram.png
- 758×390
- 2020/11/03 18:01
- 39.5 KB
- zedboard_dimensions.zip
- 2020/09/30 15:48
- 1.7 MB
- zedboard_linux_design.zip
- 2018/10/04 15:54
- 8.5 MB
- zedboard_linux_design_14_2.zip
- 2018/10/04 15:54
- 8.4 MB
- zedboard_sch.pdf
- 2016/10/13 07:49
- 2.9 MB
- zedboard_ug.pdf
- 2016/07/08 19:29
- 2.4 MB
- zed_sch_rev_f1-public.pdf
- 2020/11/12 20:09
- 3.5 MB
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