Zybo Z7 Pmod VGA Demo
This simple VGA Demo project demonstrates usage of a Pmod VGA connected to the Zybo's Pmod ports. The behavior is as follows:
- A bouncing box and black, white, and multiple colors of bars are displayed on a connected VGA monitor.
- The Pmod VGA is controlled by the Zybo through Pmod ports JC and JD.
- The screen resolution is configurable through HDL code.
- Zybo Z7 with a MicroUSB Programming Cable
- Vivado installation compatible with the latest release of this demo (2020.1)
- See Installing Vivado, Vitis, and Digilent Board Files for installation instructions.
- Pmod VGA
- VGA Monitor and cable
Download and Usage Instructions
First and foremost, releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.
The latest release version for this demo is highlighted in green.
Note: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.
|Board Variant||Release Tag||Release Downloads||Setup Instructions|
|Zybo Z7-10||10/Pmod-VGA/2020.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Zybo Z7-20||20/Pmod-VGA/2020.1-1||Release ZIP Downloads||See Using the Latest Release, below|
|Zybo Z7-10||v2018.2-1||Release ZIP Downloads||v2018.2-1 Github README|
|Zybo Z7-20||v2018.2-1||Release ZIP Downloads||v2018.2-1 Github README|
Note for Advanced Users: All demos for the Zybo Z7 are provided through the Zybo-Z7 repository on Github. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories page.
Instructions on the use of the latest release can be found in this dropdown:
- Using the Latest Release
Note: This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.
Important: These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.
First, download and extract the '*.xpr.zip' file from the demo release page, linked above.
- Open a Vivado Project from a Release
Select the dropdown corresponding to your operating system, below.
- Build a Vivado Project
Note that if your project already has a generated bitstream, as indicated by the status in the top right corner of the window reading “write_bitstream Complete!”, then you can skip this section.
Generate a Bitstream
In order to create a file that can be used to program the target board, each stage of the “compilation pipeline” needs to be run.
This starts with Synthesis. Synthesis creates a description of the logic gates and connections between them required to perform the functionality described by the HDL files, given the constraints included in XDC files. To run Synthesis click either in the toolbar or in the Flow Navigator. The output of Synthesis is then passed to Implementation.
Implementation has several steps. The steps that are always run are Opt Design (Optimize the design to fit on the target FPGA), Place Design (Lay out the design in the target FPGA fabric), and Route Design (Route signals through the fabric). To run Implementation click either in the toolbar or in the Flow Navigator. This output is then passed on to the Bitstream Generator.
The Bitstream Generator generates the final output file needed for programming the FPGA. To run Bitstream Generation click either in the toolbar or in the Flow Navigator. With no settings changed, the generator will create a '.bit' file.
Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes. When complete, a pop up dialog will appear, prompting you to select one of several options. None are relevant for the purposes of this guide, so click Cancel. The “write_bitstream complete” status message can be seen in the top right corner of the window, indicating that the demo is ready to be deployed to your board.
- Set up the Zybo Z7
Plug the microUSB programming cable into the Zybo Z7's PROG/UART port.
Connect the Pmod VGA to the JC and JD Pmod ports.
Connect the VGA Monitor to the Pmod VGA through a VGA cable.
- Program a Bitstream onto an FPGA Board
Vivado's Hardware Manager can be opened by clicking on Open Hardware Manager at the bottom of the Flow Navigator pane on the left side of the Vivado window.
The first step to programming a device is to connect the Vivado Hardware Server to it as a target. To get to the Open Hardware Target wizard click the link in the green banner near the top of the window. From the drop-down that opens, select .
Once the wizard opens, click Next.
The next screen asks if the hardware server is local or remote. If the board is connected to the host computer choose local, if it is connected to another machine choose remote and fill in the Host Name and Port fields.
Click Next to continue.
This screen gives a list of devices connected to the hardware server. If there is only one connected it will be the only device shown.
Click Next to continue.
The final screen shows a summary of the options selected in the wizard. Verify the information and click Finish. The board is now connected to the hardware server.
To program the device with the bit file generated earlier, either click the link in the green banner at the top of the window or click the button in the Flow Navigator under . From the drop-down that opens, select the device to program (Example: ) and the following window will open:
The Bitstream File field should be automatically filled in with the bit file generated earlier. If not, click the button at the right end of the field and navigate to
<Project Directory>/<Project Name>.runs/impl_1/ and select the bit file (Example: ). Now click Program. This will connect to the board, clear the current configuration, and program it using the new bit file.
1. View Results
2. Changing the Resolution
You may want to change the display resolution if your VGA monitor does not support 1080p, or you want to modify the demo for a specific application.
To select a different display resolution, select the appropriate set of Sync Generation constants for your target resolution from the list starting at line 47 of top.vhd. Uncomment the ten corresponding constants, FRAME_WIDTH through V_POL, and comment the default versions of those same constants. The default resolution is 1920×1080 @ 60Hz.
Next select Project Manager in the Flow Navigator. In the Hierarchy tab of the Sources box, expand top under Design Sources and double click on clk_div_inst. Change the clk_out1 Requested frequency - circled in red below - to the required pxl_clk frequency specified in the selected resolution's Sync Generation comment block. Select Ok, then Generate in the Generate Output Products dialog that pops up. To reprogram your board with the new hardware, return to Step 2.
All materials related to the use of the Zybo Z7 can be found on its Resource Center.
All materials related to the use of the list other products here can be found on their resource centers, linked below:
- Pmod VGA Resource Center
For a walkthrough of the process of creating a simple HDL project in Vivado, see Getting Started with Vivado for Hardware-Only Designs. Information on important parts of the GUI, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.
For technical support, please visit the FPGA section of the Digilent Forum.