Genesys ZU-5EV HDMI Demo

The Genesys ZU-5EV HDMI Demo project demonstrates usage of the Genesys ZU-5EV's HDMI in and HDMI out ports. The behavior is as follows:

• A menu is displayed over UART at 115200 baud rate.
• Information about the HDMI RX/TX Stream along with the settings for the GT transceivers and PLL can be accessed from the menu.
• When only the HDMI TX port is connected, the project enters in standalone mode, generating a color bar on the display.
• From the menu, the color bar can be forced to re-appear on the display.
• The resolution can be changed on the fly, but the user needs to make sure that he is using the correct pixel clock. More information on how to calculate the correct clock for the desired resolution can be found in the Clocking section of the HDMI TX Subsytem Product guide.
• After calculating the resolution, the IC46 (SI5342A-D-GM) needs to be reprogrammed accordingly. More information, together with two different example projects can be found in chapter 5.1 GTH Reference Clocks* from the product reference manual.
• The frame rate can be changed. The default value is 60 Hz.
• The color depth can be changed. The default value is 8bpp.
• The color space can be changed. The default color space is RGB.
• When both HDMI ports are connected, and there is a valid HDMI source, the project will automatically enter in pass-through mode and the Si5342A-D-GM will generate a jitter-attenuated reference clock to drive the HDMI Transmitter Subsystem with a phase-aligned version of the HDMI RX Subsystem HDMI RX TMDS Clock. Thus, the image from the HDMI source will be outputted on the display.
• The pass-trough mode can be forced from the menu.
• There is a GT & HDMI TX/RX log option that can be used for debugging. For example, for the HDMI TX log, each message is bonded to a specific interrupt. Thus, for debugging, the entire chain of events can be reiterated and compared with the one listed in HDMI TX Subsytem Product Guide, Appendix D: Application Software Development.
• The EDID can be set and displayed.
• The audio can be muted/unmuted and each audio channel can be reconfigured.
• The output video pattern can be changed. The default setting is for color bar.
• The TX mode can be forced in HDMI or DVI.

• Genesys ZU-5EV FPGA board
• 1 Micro-USB cables
• Genesys ZU-5EV Power Supply
• 1 or 2 HDMI-HDMI or HDMI-DVI Cables
• 1 HDMI Display
• 1 HDMI Source (Used only in pass-through mode)

First and foremost, any user can access this demo using two different approaches. The first one is by importing the release archive through Vitis GUI. This method doesn't have great portability, and for that, the user needs to go through extra steps and workarounds to build the project. The second one is by cloning the project. This is a fast and reliable method for running this demo, with only one downside for Windows systems. And that is the need to install a bash emulation tool to run all the specific commands. This document provides support for both methods.

Note: Releases - consisting of a set of files for download - are only compatible with a specific version of the Xilinx tools, as specified in the name of the release (referred to as a release tag). In addition, releases are only compatible with the specified variant of the board. For example, a release tagged “20/DMA/2020.1” for the Zybo Z7 is only to be used with the -20 variant of the board and Vivado 2020.1.

The latest release version for this demo is highlighted in green.

Important: Releases for FPGA demos from before 2020.1 used a different git structure, and used a different release tag naming scheme.

Note for Advanced Users: GitHub sources for this demo can be found in the 5ev/demo/hdmi branch of the Genesys-ZU repository. Further documentation on the structure of this repository can be found on this wiki's Digilent FPGA Demo Git Repositories page.

Instructions on the use of the latest release can be found in this dropdown:

Using the Latest Release

Note: This workflow is common across many Digilent FPGA demos. Screenshots may not match the demo you are working with.

Important: These steps are only to be used with releases for Xilinx tools versions 2020.1 and newer. Older releases may require other flows, as noted in the table of releases.

First, download the '*.xpr.zip' and '*.ide.zip' files from the demo release, linked above. The XPR archive contains the Vivado project used to build the hardware platform for this demo. The project can be opened, modified, and used to update the hardware platform later if so desired, but this is optional. The IDE archive contains a set of projects to be imported into a Vitis workspace.

Note: Unlike with Vivado XPR archives, do NOT extract the Vitis project archive ('*.ide.xip'). Vitis imports sources from the archive file directly.

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Import Vitis Projects from a Release

Select the dropdown corresponding to your operating system, below.

Windows

Open Vitis through the start menu or desktop shortcut created during the installation process.

Linux

Open a terminal and run the following commands. The install path is /opt/Xilinx by default.

source <install_path>/Vitis/2020.1/settings64.sh
vitis

Note: Regardless of OS, if Vivado is open, Vitis can also be launched through the Tools → Launch Vitis toolbar option.

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Upon launching Vitis, a dialog will appear where a workspace must be chosen. The workspace is the directory where all of the projects and files for the application being developed will live. If a folder that does not currently exist is chosen, it will be created. Choose a workspace and click Launch to finish launching Vitis.

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With Vitis open, click the Import Project button to import projects from a Vitis project exported zip file, then navigate to and select the IDE zip file you downloaded.

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Make sure each project in the archive is checked, then click Finish to import them into your workspace.

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Build a Vitis Application

Once an application project has been set up and includes all necessary sources, it should be built. To build the project and all of its dependencies, select the [System] project in the Assistant pane, and either click the Build button (), or press Ctrl-B on your keyboard.

Note: There are three types of build targets in the Assistant pane, Platforms, Systems, and Applications. Building the application will not trigger any other applications in the system to be built, but will build the wrapper as a dependency. Building the platform will only build the platform, as it has no dependencies. Building the system causes each application in the system, as well as the platform, to be built.

This process may take several minutes to complete. When done, the Console tab at the bottom of the window will display a “Build Finished” message.

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Set up the Genesys ZU-5EV

Set up the Genesys ZU-5EV for Standalone Mode

Plug the HDMI cable into the HDMI TX port of the Genesys ZU. Connect one end of the cable to the HDMI TX port, and the other one to a DVI or HDMI port of your monitor. This cable does not need to be connected until the demo is running, but it is recommended to set it up now. Please see image bellow.

Figure 1: HDMI Cable Connections in standalone mode Plug the microUSB programming cable into the Genesys ZU-5EV's PROG/UART port.

Set up the Genesys ZU-5EV for Pass-Through Mode

Connect the HDMI cables to the HDMI ports of the Genesys ZU. Connect one end of the first cable to the HDMI TX port, and the other one to a DVI or HDMI port of your monitor. Then, connect one end of the second cable to the HDMI RX port, and the other end to your HDMI source. These cables do not need to be connected until the demo is running, but it is recommended to set them up now. Please see image bellow.

Figure 2: HDMI Cable Connections in pass-through mode Plug the microUSB programming cable into the Genesys ZU-5EV's PROG/UART port.

Launch the Vitis Baremetal Software Application

First, many applications require that a serial console is connected to the board, so that standard output (from print statements) can be viewed. For this purpose, a serial terminal should be used. Use a serial terminal application to connect to the board's serial port. Unless otherwise stated, Zynq designs use a baud rate of 115200 and Microblaze designs with an AXI UART Lite IP use a baud rate of 9600.

Note: While Vitis has a built in serial terminal included in its Debug view, it sends characters to a board on a line-by-line basis. Some software examples require the use of character-by-character reception of data. Tera Term or PuTTY are recommended if you are not sure what will work.

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Browse for the 5ev_fsbl.elf file. The hw platform comes without generating its boot components, so the user needs to manually select a valid boot elf file. Double Click on platform.spr → Browse to the project workspace folder that was previously selected, and double click on 5ev_fsbl → Release → 5ev_fsbl.elf → and then click Open.

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Click on Project and select Build Project, or simply press CTRL+B. The build should take a couple of seconds.

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In the Explorer pane at the left side of the screen, right click on the application or system project that is to be run, and select Run as → 1 Launch on Hardware . The FPGA will be programmed with the bitstream, the ELF file previously selected is loaded into system memory, and the application project will begin to run. You will need to click back over to the Vitis Serial Terminal from the Console tab.

Note: Once the project has been run at least once, you can use the green run button () in the toolbar at the top of the screen to program the board instead.

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At this point, the demo is now running on your board. Refer to the Description section of this document for more information on what it does.

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Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.

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In order to modify and switch out the hardware platform for a baremetal demo, you should first open the Vivado project from the release. Extract the previously downloaded '*.xpr.zip' file.

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In order to modify and switch out the hardware platform for a baremetal demo, you should first open the Vivado project from the release. Extract the previously downloaded '*.xpr.zip' file.

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Open a Block Design Project in Vivado

Launch Vivado

Select the dropdown corresponding to your operating system, below.

Windows

Open Vivado through the start menu or desktop shortcut created during the installation process.

Linux

Open a terminal, and change directory (cd) to a folder where log files for your Vivado session can be placed, then run the following commands:

source <install_path>/Vivado/<version>/settings64.sh
vivado

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In Vivado's welcome screen, use the Open Project button to navigate to and open the XPR file contained in the folder the release was extracted into.

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The project's block diagram, which contains the design, with all of the existing components and their connections, can be opened by either double-clicking on the “*.bd” file in the sources pane (which also includes other source files, such as constraints), or by clicking the Open Block Design button in the Flow Navigator pane.

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Making changes to the design is out of the scope of this particular document. More information on how to use IP Integrator to create or modify a project can be found through Getting Started with Vivado and Vitis for Baremetal Software Projects. The remainder of this document will discuss how to generate a bitstream, export a new hardware platform, and load it into Vitis.

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Before the Vivado project can be built, the block design must be validated. This step runs an automatic check of the block design to see if there are any potential issues with it. Click the Validate Design button () in the Diagram pane's toolbar (or press the F6 key).

If the design has issues, a dialog will pop up that lists them. It should be noted that most Warnings can be ignored, as can some Critical Warnings. These issues can also be viewed in the Messages tab of the pane at the bottom of the window.

If there are no issues, a dialog will pop up that will tell you so. Click OK to continue.

Note: Some Zynq boards may produce critical warnings at this stage relating to PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY parameters. These warnings are ignorable and will not affect the functionality of the project. See the Hardware Errata section of your board's reference manual for more information.

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Build a Vivado Project

At this point, the Vivado Project is ready to be built, by running it through Synthesis and Implementation, and finally generating a bitstream. Click the Generate Bitstream button in the Program and Debug section of the Flow Navigator pane at the left side of the window.

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A dialog will pop up with several options for how Synthesis and Implementation should be run. Most should be left as defaults. Of particular importance is the Number of jobs dropdown, which is used to specify how much of the resources of your computer should be dedicated to the build. A larger number of jobs will dedicate more resources, which will allow the build to be completed faster. It is recommended to choose the highest available number.

Note: Critical warnings about how IPs included within another IP were packaged with a different board value can be safely ignored. The same is true for warnings related to negative CK-to-DQS delays seen on some Zynq boards.

Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes.

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When complete, a dialog will pop up that presents several options for what to do next:

• Open Implemented Design can be used to view the actual hardware design that has been implemented and will be placed onto the chip.
• View Reports can be used to view additional information about the design, including how much of the resources of the FPGA will be used by the design.
• Open Hardware Manager can be used to go directly to Vivado's Hardware Manager, which can be used to program a hardware design onto a board. This is typically used for designs that do not involve a software component.
• Generate Memory Configuration File can be used to create a file for programming an FPGA-only design into flash memory.

If none of these options are desired, click Cancel to continue.

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Export a Hardware Platform

Once the project has been built, the design must be exported from Vivado so that Vitis has access to information about the hardware that a software application is being developed for. This includes the set of IP connected to the processor, their drivers, their addresses, and more. Exporting hardware after the bitstream has been generated allows you to program your board directly from within Vitis.

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To export the hardware design, click Export → Export Hardware in the File menu.

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The wizard that pops up guides you through the options available for hardware export. The first screen allows you to select a Fixed or Expandable platform. In this case, choose a Fixed platform and click Next to continue.

This screen is not present in Vivado 2022.1, proceed to the next

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The Output screen allows you to select whether only the hardware specification (Pre-synthesis) should be exported, or whether the bitstream should be included. Since the bitstream has already been generated, it should be included in the platform so that Vitis can automatically figure out where it is when programming a board. Select Include bitstream and click Next to continue.

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The Files screen gives you the option to choose a name for the Xilinx Shell Architecture (XSA) file, and provide a path to a folder that the file will be placed within. Give your XSA file a name, and choose a memorable location to place it in. This file will later be imported into Vitis, so take a note of where it is placed and what it is called.

Important: Do not use spaces in the file name or export path. Underscores or camelCase are recommended instead.

Click Next to continue.

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The final screen of the wizard summarizes the options you selected. Click Finish.

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Update a Hardware Platform in Vitis

If a hardware design is changed after having created a Vitis application project, several steps must be taken in order to update the Vitis workspace with a newly exported XSA file. The XSA file contains all of the information relevant to Vitis about the hardware platform, and changing a platform project's specification based on this file will automatically load in any changes. This includes adding new drivers for new IP that have been installed and changing the files that define the addresses and other details of any installed IP that may have been renamed or had their addresses changed.

These steps assume that you have already regenerated the bitstream and reexported hardware in the same way that would be done prior to creating a new Vitis workspace.

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Within Vitis' Assistant pane, find the platform project that you wish to update with the new hardware. This project will typically have a name that ends with “_wrapper”, and is marked with the text “[Platform]”.

Right click on this project and select Update Hardware Specification.

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In the dialog that pops up, click Browse, and navigate to the location of the XSA file that you want the platform to target. Click Open to select this file.

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Double check that the Hardware Specification File path matches that of the XSA file you want to use, then click OK to start the automatic process of updating the platform.

When complete, a dialog will pop up to state that the platform project has been updated. Click OK to acknowledge this.

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At this point, changes to the hardware specification have been loaded into the hardware platform. The bitstream will have been updated, if it was loaded into the XSA file. The set of drivers and the xparameters file will have changed to match what is in the modified design. Changes to the software application may be required before the application can be built and programmed onto the board, however, detailing what may need to be done is outside of the scope of this guide.

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Instructions on the cloning and the use of the latest git project can be found in this dropdown:

Using the Genesys ZU repository

Important: These steps are only to be used with Xilinx tools versions 2020.1 and newer.

Note for Advanced Users: Further documentation on the structure of the Genesys ZU repository can be found on this wiki's Digilent FPGA Demo Git Repositories page.

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Git for Windows

For Windows OS we need to emulate Git from command line. For this please download and install Git SCM for Windows.

Clone the project repository and initialize all the submodules.

First, copy the https or ssh URL from Genesys ZU repository.

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Create a folder, in a location of your choice on the computer. Right-click from within and select Git Bash Here

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First, we have to clone the root repository. For this, please run the fallowing command.

git clone [email protected]:Digilent/Genesys-ZU.git

Navigate inside the repository.

cd Genesys-ZU/

We use se the following commands within the root repository to check out the “5ev/hdmi/demo” branch, and update the submodules to the correct commits:

git checkout 5ev/demo/hdmi

git submodule init

git submodule update

Navigate to the “../sw” folder.

cd sw/

Initialize and update the embeddedsw submodule.

git submodule init

git submodule update

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Recreate a Vitis Workspace from Source

Important: When selecting a workspace to open Vitis into, the use of the extracted software archive's “ws” folder is recommended. The use of this folder simplifies the process of invoking the script that recreates the projects.

Select the dropdown corresponding to your operating system, below.

Windows

Open Vitis through the start menu or desktop shortcut created during the installation process.

Linux

Open a terminal and run the following commands. The install path is /opt/Xilinx by default.

source <install_path>/Vitis/2020.1/settings64.sh
vitis

Note: Regardless of OS, if Vivado is open, Vitis can also be launched through the Tools → Launch Vitis toolbar option.

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Upon launching Vitis, a dialog will appear where a workspace must be chosen. The workspace is the directory where all of the projects and files for the application being developed will live. If a folder that does not currently exist is chosen, it will be created. Choose a workspace and click Launch to finish launching Vitis.

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With Vitis open, in the menu bar at the top of the window, use the Xilinx → XSCT Console option to launch the Xilinx Software Command-line Tool.

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In the XSCT Console, if you used the software archive's ws folder, enter the command below to run a script that recreates each of the projects and platforms associated with the demo from their sources.

source [getws]/../src/checkout.tcl

If you did not use the ws folder, find the path to the extracted archive, and enter the commands below. Note that all slashes in the path must be forward slashes (“/”) or the entire path must be enclosed in curly braces (“{}”).

source (path to software)/src/checkout.tcl

The checkout process may some time, though not more than a few minutes, as the projects are recreated and built. When complete, the “xsct%” prompt will reappear.

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Set up the Genesys ZU-5EV

Set up the Genesys ZU-5EV for Standalone Mode

Plug the HDMI cable into the HDMI TX port of the Genesys ZU. Connect one end of the cable to the HDMI TX port, and the other one to a DVI or HDMI port of your monitor. This cable does not need to be connected until the demo is running, but it is recommended to set it up now. Please see image bellow.

Figure 1: HDMI Cable Connections in standalone mode Plug the microUSB programming cable into the Genesys ZU-5EV's PROG/UART port.

Set up the Genesys ZU-5EV for Pass-Through Mode

Connect the HDMI cables to the HDMI ports of the Genesys ZU. Connect one end of the first cable to the HDMI TX port, and the other one to a DVI or HDMI port of your monitor. Then, connect one end of the second cable to the HDMI RX port, and the other end to your HDMI source. These cables do not need to be connected until the demo is running, but it is recommended to set them up now. Please see image bellow.

Figure 2: HDMI Cable Connections in pass-through mode Plug the microUSB programming cable into the Genesys ZU-5EV's PROG/UART port.

Launch the Vitis Baremetal Software Application

First, many applications require that a serial console is connected to the board, so that standard output (from print statements) can be viewed. For this purpose, a serial terminal should be used. Use a serial terminal application to connect to the board's serial port. Unless otherwise stated, Zynq designs use a baud rate of 115200 and Microblaze designs with an AXI UART Lite IP use a baud rate of 9600.

Note: While Vitis has a built in serial terminal included in its Debug view, it sends characters to a board on a line-by-line basis. Some software examples require the use of character-by-character reception of data. Tera Term or PuTTY are recommended if you are not sure what will work.

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Browse for the 5ev_fsbl.elf file. The hw platform comes without generating its boot components, so the user needs to manually select a valid boot elf file. Double Click on platform.spr → Browse to the project workspace folder that was previously selected, and double click on 5ev_fsbl → Release → 5ev_fsbl.elf → and then click Open.

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Click on Project and select Build Project, or simply press CTRL+B. The build should take a couple of seconds.

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In the Explorer pane at the left side of the screen, right click on the application or system project that is to be run, and select Run as → 1 Launch on Hardware . The FPGA will be programmed with the bitstream, the ELF file previously selected is loaded into system memory, and the application project will begin to run. You will need to click back over to the Vitis Serial Terminal from the Console tab.

Note: Once the project has been run at least once, you can use the green run button () in the toolbar at the top of the screen to program the board instead.

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At this point, the demo is now running on your board. Refer to the Description section of this document for more information on what it does.

---

Additional steps beyond here present how you can use the other archive provided in the release, containing the hardware project, to rebuild the Vivado project, and use a newly exported XSA file to update the platform in Vitis.

---

In order to modify and switch out the hardware platform for a baremetal demo, you should first open the Vivado project from the release. Extract the previously downloaded '*.xpr.zip' file.

---

In order to modify and switch out the hardware platform for a baremetal demo, you should first open the Vivado project from the release. Extract the previously downloaded '*.xpr.zip' file.

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Open a Block Design Project in Vivado

Launch Vivado

Select the dropdown corresponding to your operating system, below.

Windows

Open Vivado through the start menu or desktop shortcut created during the installation process.

Linux

Open a terminal, and change directory (cd) to a folder where log files for your Vivado session can be placed, then run the following commands:

source <install_path>/Vivado/<version>/settings64.sh
vivado

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In Vivado's welcome screen, use the Open Project button to navigate to and open the XPR file contained in the folder the release was extracted into.

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The project's block diagram, which contains the design, with all of the existing components and their connections, can be opened by either double-clicking on the “*.bd” file in the sources pane (which also includes other source files, such as constraints), or by clicking the Open Block Design button in the Flow Navigator pane.

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Making changes to the design is out of the scope of this particular document. More information on how to use IP Integrator to create or modify a project can be found through Getting Started with Vivado and Vitis for Baremetal Software Projects. The remainder of this document will discuss how to generate a bitstream, export a new hardware platform, and load it into Vitis.

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Before the Vivado project can be built, the block design must be validated. This step runs an automatic check of the block design to see if there are any potential issues with it. Click the Validate Design button () in the Diagram pane's toolbar (or press the F6 key).

If the design has issues, a dialog will pop up that lists them. It should be noted that most Warnings can be ignored, as can some Critical Warnings. These issues can also be viewed in the Messages tab of the pane at the bottom of the window.

If there are no issues, a dialog will pop up that will tell you so. Click OK to continue.

Note: Some Zynq boards may produce critical warnings at this stage relating to PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY parameters. These warnings are ignorable and will not affect the functionality of the project. See the Hardware Errata section of your board's reference manual for more information.

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Build a Vivado Project

At this point, the Vivado Project is ready to be built, by running it through Synthesis and Implementation, and finally generating a bitstream. Click the Generate Bitstream button in the Program and Debug section of the Flow Navigator pane at the left side of the window.

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A dialog will pop up with several options for how Synthesis and Implementation should be run. Most should be left as defaults. Of particular importance is the Number of jobs dropdown, which is used to specify how much of the resources of your computer should be dedicated to the build. A larger number of jobs will dedicate more resources, which will allow the build to be completed faster. It is recommended to choose the highest available number.

Note: Critical warnings about how IPs included within another IP were packaged with a different board value can be safely ignored. The same is true for warnings related to negative CK-to-DQS delays seen on some Zynq boards.

Depending on the complexity of the design, the board used, and the strength of your computer, the process of building the project can take between 5 and 60 minutes.

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When complete, a dialog will pop up that presents several options for what to do next:

• Open Implemented Design can be used to view the actual hardware design that has been implemented and will be placed onto the chip.
• View Reports can be used to view additional information about the design, including how much of the resources of the FPGA will be used by the design.
• Open Hardware Manager can be used to go directly to Vivado's Hardware Manager, which can be used to program a hardware design onto a board. This is typically used for designs that do not involve a software component.
• Generate Memory Configuration File can be used to create a file for programming an FPGA-only design into flash memory.

If none of these options are desired, click Cancel to continue.

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Export a Hardware Platform

Once the project has been built, the design must be exported from Vivado so that Vitis has access to information about the hardware that a software application is being developed for. This includes the set of IP connected to the processor, their drivers, their addresses, and more. Exporting hardware after the bitstream has been generated allows you to program your board directly from within Vitis.

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To export the hardware design, click Export → Export Hardware in the File menu.

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The wizard that pops up guides you through the options available for hardware export. The first screen allows you to select a Fixed or Expandable platform. In this case, choose a Fixed platform and click Next to continue.

This screen is not present in Vivado 2022.1, proceed to the next

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The Output screen allows you to select whether only the hardware specification (Pre-synthesis) should be exported, or whether the bitstream should be included. Since the bitstream has already been generated, it should be included in the platform so that Vitis can automatically figure out where it is when programming a board. Select Include bitstream and click Next to continue.

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The Files screen gives you the option to choose a name for the Xilinx Shell Architecture (XSA) file, and provide a path to a folder that the file will be placed within. Give your XSA file a name, and choose a memorable location to place it in. This file will later be imported into Vitis, so take a note of where it is placed and what it is called.

Important: Do not use spaces in the file name or export path. Underscores or camelCase are recommended instead.

Click Next to continue.

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The final screen of the wizard summarizes the options you selected. Click Finish.

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Update a Hardware Platform in Vitis

If a hardware design is changed after having created a Vitis application project, several steps must be taken in order to update the Vitis workspace with a newly exported XSA file. The XSA file contains all of the information relevant to Vitis about the hardware platform, and changing a platform project's specification based on this file will automatically load in any changes. This includes adding new drivers for new IP that have been installed and changing the files that define the addresses and other details of any installed IP that may have been renamed or had their addresses changed.

These steps assume that you have already regenerated the bitstream and reexported hardware in the same way that would be done prior to creating a new Vitis workspace.

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Within Vitis' Assistant pane, find the platform project that you wish to update with the new hardware. This project will typically have a name that ends with “_wrapper”, and is marked with the text “[Platform]”.

Right click on this project and select Update Hardware Specification.

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In the dialog that pops up, click Browse, and navigate to the location of the XSA file that you want the platform to target. Click Open to select this file.

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Double check that the Hardware Specification File path matches that of the XSA file you want to use, then click OK to start the automatic process of updating the platform.

When complete, a dialog will pop up to state that the platform project has been updated. Click OK to acknowledge this.

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At this point, changes to the hardware specification have been loaded into the hardware platform. The bitstream will have been updated, if it was loaded into the XSA file. The set of drivers and the xparameters file will have changed to match what is in the modified design. Changes to the software application may be required before the application can be built and programmed onto the board, however, detailing what may need to be done is outside of the scope of this guide.

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After every Platform Specification update, please make sure you follow these steps, to ensure the Platform Specification changes are correctly applied to your software project:

1. Open 5ev_hw_pf → platform.spr and make sure the FSBL file location is correctly set ([..]\ws\5ev_fsbl\Release\5ev_fsbl.elf).
2. Right click on 5ev_hw_pf and select Update Hardware Specification. Make sure the path is correct ([..]/sw/src/5ev_hw_pf/system_wrapper.xsa).
3. Right click on 5ev_hw_pf and select Build Project.
4. Right click on 5ev_boot and select Build Project.
5. Genesys ZU workspaces externalize FSBL into a stand-alone application project to work around the wrong FSBL BSP optimization flag bug when it is generated as part of a hardware platform project. The ZynqMP FSBL is a template project that gets recreated upon checkout with local copies of sources from the local “embeddedsw” fork and the hardware platform. The “psu_init.*” files are copied and not linked from the platform. Therefore, after every platform specification update the “psu_init.*” files in [3eg|5ev]_fsbl/src need to be manually overwritten from the built platform project directory [3eg|5ev]_hw_pf/export/[3eg|5ev]_hw_pf/hw/.
6. Right click on 5ev_boot and select Build Project.
7. If you still encounter an error saying that fsbl.elf is not found, copy the [..]\ws\5ev_fsbl\Release\5ev_fsbl.elf file to [..]\ws\5ev_hw_pf\export\5ev_hw_pf\sw\5ev_hw_pf\boot\, renaming it to fsbl.elf and overwriting the existing file, if it does exist. Then right click on 5ev_boot and select Build Project again.
8. Right click on 5ev_master_system and select Build Project.

In standalone mode you should see the fallowing color bar.

In pass-through mode, you should see the HDMI image generated by the HDMI Source. For example, in cases in which the HDMI source is a laptop, you should see, depending on the case, the laptop display being duplicated or extended.

If your serial monitor (Tera Term, etc.) was open and it was correctly configured to work with a baud rate of 115200, you should see the following menu when the program starts up.


Note: You can connect your serial terminal to your board before the board is programmed, this will make sure that you don't miss any startup messages. If the demo is already running, and you cannot see the startup messages, press “ENTER”. This will refresh the menu messages.

You can select each individual option by clicking on its corresponding letter.

All materials related to the use of the Genesys ZU can be found on its Resource Center.

For a walkthrough of the process of creating a simple baremetal software project in Vivado and Vitis, see Getting Started with Vivado and Vitis for Baremetal Software Projects. Information on important parts of the GUIs, and indirect discussion of the steps required to modify, rebuild, and run this demo in hardware can also be found here.

For technical support, please visit the FPGA section of the Digilent Forum.