Pmod BB
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Reference Manual
Technical Support
Pmod BB
Wire Wrap / Breadboard
Features
- 266 tie point wire wrap area
- 170 tie point solderless breadboard
- Jumper blocks to tie the power pins together
- Additional Pmod host port
- 12-pin connector, all signals pass through
Electrical
Bus
GPIO
Specification Version
1.2.0
Logic Level
3.3V
Physical
Width
3.5 in (8.89 cm)
Length
1.5 in (3.81 cm)
J1 & J2 Pinout
Pin 1
P1
Pin 2
P2
Pin 3
P3
Pin 4
P4
Pin 5
GA
Pin 6
VA
Pin 7
P7
Pin 8
P8
Pin 9
P9
Pin 10
P10
Pin 11
GA
Pin 12
VA
J3 & J4 Pinout
Pin 1
P1
Pin 2
P2
Pin 3
P3
Pin 4
P4
Pin 5
GB
Pin 6
VB
Pin 7
P7
Pin 8
P8
Pin 9
P9
Pin 10
P10
Pin 11
GB
Pin 12
VB
Example Projects
Microprocessor
Programmable Logic
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- Digilent Pmod IPs are only supported in Vivado and Xilinx SDK versions 2019.1 and earlier.
Additional Resources
- Specification Version 1.2.0: PDF