PmodIA User Guide

This user guide is (clearly) not completed yet, but I found that the reference manual I was writing was getting way too long explaining how one might measure the impedance of a discreet component/circuit and providing the associated data streams that would be needed.

So, I have instead relocated the text to this user guide for people who are interested in what they might need to do if they did not want to use/cannot use the associated MPIDE library.

Here I outline a process for calculating an unknown impedance value.

Before any useful calculations can occur, users must first calculate the gain factor associated with the PmodIA. To do this, users need first set the AD5933 into standby mode and the PGA gain to 1, choose an output excitation voltage and calibration frequency, and choose a known calibration impedance value such as 200 kΩ to place between the two SMA connectors. The default Master Clock Rate (MCLK) that is used internally by the PmodIA is 16.776 MHz.

The 24-bit value that represents the desired calibration frequency can be determined from the equation below:

The set of registers and their associated bits that need to be written to to accomplish this are provided below:

¹ – Don't Care bit
² – 0 and 0 result in a 2V peak to peak range, 0 and 1 result in a 200 mV peak to peak range, 1 and 0 result in a 400 mV peak to peak range, 1 and 1 result in a 1V peak to peak range

Once the desired frequency is programmed into the PmodIA, users can program the module to Initialize with Start Frequency to allow the frequency generator to reach steady state; the time frame to wait for the frequency generator to reach steady state is entirely decided by the user, as per AD5933 reference manual. Once that time period has passed, users may issue a Start Frequency Sweep command. The internal ADC will sample the measured impedance after a set number of settling time cycles have passed and store the processed result in the Real and Imaginary Data registers.

The set of registers that need to be written to or read to successfully obtain the impedance information, including programming the number of settling time cycles is provided below:

¹ – Don't Care bit
² – 0 and 0 result in a 2V peak to peak range, 0 and 1 result in a 200 mV peak to peak range, 1 and 0 result in a 400 mV peak to peak range, 1 and 1 result in a 1V peak to peak range

Naturally, some time is required for the DFT to be performed on the received data. Users can continuously poll the Status register to determine when the DFT is complete or can wait a calculated amount of time based on the number of Settling Time cycles before confirming the DFT is complete. The equation used to calculate the settling time is provided below:

If bit D2 is at a logic level high voltage state, this indicates that the DFT is complete and the data present in the Real and Imaginary data registers are valid, allowing users to perform a block read on the two 16-bit registers.

The data registers are arranged in a two's-complement format. A reference calculation to determine the decimal value of the data is provided below:

Once the data has been obtained, the gain factor can be calculated as follows:

Once the gain factor has been determined, any other unknown impedance can then be calculated by the following equation:

The calculated gain factor will remain valid for as long as the following parameters are not changed:

• Current-to-voltage gain setting resistor (unlikely to change unless the resistor is physically removed from the Pmod)
• Output Excitation voltage
• PGA gain

A frequency sweep can also be set up. The equation to do so is provided below:

Calculating the phase……to be added in the future since I decided to keep working on other reference manuals. Until then please look at Measuring the Phase Across an Impedance section in the AD5933 Reference Manual starting on page 19.

A list of commonly used Registers and Commands as well as some of their commonly used values taken from the AD5933 datasheet starting from page 23 is provided below:

Note¹ – X is a don't care bit
Note² – The two Y bits correspond to the output voltage range where '0' and '0' result in a 2V peak to peak range, '0' and '1' result in a 200 mV peak to peak range, '1' and '0' result in a 400 mV peak to peak range, '1' and '1' result in a 1V peak to peak range
Note³ – Z is the PGA gain bit where '0' corresponds to a gain of 5 and '1' responds to a gain of 1
Note⁴ – '0' and '0' leave the number of Settling Time Cycles as is, '0' and '1' double the set number of Settling Time Cycles, '1' and '0' is reserved, '1' and '1' quadruple the number of Settling Time Cycles

Users can load their own crystal oscillator from the recommended packages on the PmodIA schematic. To do so, users likely need to change out the capacitors C7 and C11 and the resistor R8. The package size for both of the capacitors is 0603 and the package size for the resistor is 0402.