TABLE OF CONTENTS

Overview
Block Diagram
External Ports
Processor
   microblaze_0
          memory map
Debuggers
   mdm_0
Busses
   dlmb
   ilmb
   mb_plb
Memory
   lmb_bram
Memory Controllers
   dlmb_cntlr
   ilmb_cntlr
Peripherals
   LED_7SEGMENT
   LEDs_8Bit
   Push_Buttons_3Bit
   RS232_PORT
   Switches_8Bit
   proc_sys_reset_0
IP
   clock_generator_0
Timing Information
Overview TOC
Resources Used
1   MicroBlaze
1   Processor Local Bus (PLB) 4.6
2   Local Memory Bus (LMB) 1.0
1   Block RAM (BRAM) Block
2   LMB BRAM Controller
4   XPS General Purpose IO
1   XPS UART (Lite)
1   Clock Generator
1   MicroBlaze Debug Module (MDM)
1   Processor System Reset Module
Specifics
Generated Thu Aug 06 10:53:39 2009
EDK Version 11.1
Device Family spartan3e
Device xc3s500efg320-4

Block Diagram TOC

BlockDiagram
External Ports TOC

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
LED_7SEGMENT fpga_0_LED_7SEGMENT_GPIO_IO_O_pin O 0:11 fpga_0_LED_7SEGMENT_GPIO_IO_O_pin
LEDs_8Bit fpga_0_LEDs_8Bit_GPIO_IO_O_pin O 0:7 fpga_0_LEDs_8Bit_GPIO_IO_O_pin
Push_Buttons_3Bit fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin I 0:2 fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin
RS232_PORT fpga_0_RS232_PORT_RX_pin I 1 fpga_0_RS232_PORT_RX_pin
RS232_PORT fpga_0_RS232_PORT_TX_pin O 1 fpga_0_RS232_PORT_TX_pin
Switches_8Bit fpga_0_Switches_8Bit_GPIO_IO_I_pin I 0:7 fpga_0_Switches_8Bit_GPIO_IO_I_pin
clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 dcm_clk_s  CLK 
proc_sys_reset_0 fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET 


Processors TOC

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor

IP Specs
Core Version Documentation
microblaze 7.20.a IP DRIVER


microblaze_0 IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 MB_RESET I 1 mb_reset
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
DLMB MASTER LMB dlmb dlmb_cntlr
ILMB MASTER LMB ilmb ilmb_cntlr
DPLB MASTER PLBV46 mb_plb LEDs_8Bit
IPLB MASTER PLBV46 mb_plb LEDs_8Bit
DEBUG TARGET XIL_MBDEBUG2 microblaze_0_mdm_bus mdm_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY spartan3e
C_INSTANCE microblaze_0
C_DCACHE_BASEADDR
D-Cache Base Address
0x00000000
C_DCACHE_HIGHADDR
D-Cache High Address
0x3FFFFFFF
C_ICACHE_BASEADDR
I-Cache Base Address
0x00000000
C_ICACHE_HIGHADDR
I-Cache High Address
0x3FFFFFFF
C_ADDR_TAG_BITS
Number of I-Cache Address Tag Bits
17
C_ALLOW_DCACHE_WR
Enable D-Cache Writes
1
C_ALLOW_ICACHE_WR
Enable I-Cache Writes
1
C_AREA_OPTIMIZED
Select implementation to optimize area (with lower instruction throughput)
1
C_CACHE_BYTE_SIZE
Size of the I-Cache in Bytes
8192
C_DATA_SIZE 32
C_DCACHE_ADDR_TAG
Number of D-Cache Address Tag Bits
17
C_DCACHE_ALWAYS_USED
Use Cache Links for All D-Cache Memory Accesses
0
C_DCACHE_BYTE_SIZE
Size of D-Cache in Bytes
8192
C_DCACHE_INTERFACE 0
C_DCACHE_LINE_LEN
Data Cache Line Length
4
C_DCACHE_USE_FSL 1
C_DCACHE_USE_WRITEBACK
Enable Write-back Storage Policy
0
C_DEBUG_ENABLED
Enable MicroBlaze Debug Module Interface
1
C_DIV_ZERO_EXCEPTION
Enable Integer Divide-by-zero Exception
0
C_DOPB_BUS_EXCEPTION
Enable Data-side OPB Exception
0
C_DPLB_BURST_EN 0
C_DPLB_BUS_EXCEPTION
Enable Data-side PLB Exception
0
C_DPLB_DWIDTH 32
C_DPLB_NATIVE_DWIDTH 32
C_DPLB_P2P 0
C_DYNAMIC_BUS_SIZING 1
C_D_LMB 1
C_D_OPB 1
C_D_PLB 0
C_EDGE_IS_POSITIVE
Sense Interrupt on Rising vs. Falling Edge
1
C_FPU_EXCEPTION
Enable Floating Point Unit Exceptions
0
C_FSL_DATA_SIZE 32
C_FSL_EXCEPTION
Enable FSL Exception
0
C_FSL_LINKS
Number of FSL Links
0
C_ICACHE_ALWAYS_USED
Use Cache Links for All I-Cache Memory Accesses
0
C_ICACHE_INTERFACE 0
C_ICACHE_LINE_LEN
Instruction Cache Line Length
4
C_ICACHE_USE_FSL 1
 
Name Value
C_ILL_OPCODE_EXCEPTION
Enable Illegal Instruction Exception
0
C_INTERCONNECT
Select Processor Local Bus (PLB) interface
1
C_INTERRUPT_IS_EDGE
Sense Interrupt on Edge vs. Level
0
C_IOPB_BUS_EXCEPTION
Enable Instruction-side OPB Exception
0
C_IPLB_BURST_EN 0
C_IPLB_BUS_EXCEPTION
Enable Instruction-side PLB Exception
0
C_IPLB_DWIDTH 32
C_IPLB_NATIVE_DWIDTH 32
C_IPLB_P2P 0
C_I_LMB 1
C_I_OPB 1
C_I_PLB 0
C_MMU_DTLB_SIZE
Data Shadow Translation Look-Aside Buffer Size
4
C_MMU_ITLB_SIZE
Instruction Shadow Translation Look-Aside Buffer Size
2
C_MMU_TLB_ACCESS
Enable Access to Memory Management Special Registers
3
C_MMU_ZONES
Number of Memory Protection Zones
16
C_NUMBER_OF_PC_BRK
Number of PC Breakpoints
1
C_NUMBER_OF_RD_ADDR_BRK
Number of Read Address Watchpoints
0
C_NUMBER_OF_WR_ADDR_BRK
Number of Write Address Watchpoints
0
C_OPCODE_0x0_ILLEGAL
<qt>Generate Illegal Instruction Exception for NULL Instruction</qt>
0
C_PVR
Specifies Processor Version Register
0
C_PVR_USER1
Specify USER1 Bits in Processor Version Register
0x00
C_PVR_USER2
Specify USER2 Bits in Processor Version Registers
0x00000000
C_RESET_MSR
Specify Reset Value for Select MSR Bits
0x00000000
C_SCO 0
C_UNALIGNED_EXCEPTIONS
Enable Unaligned Data Exception
0
C_USE_BARREL
Enable Barrel Shifter
0
C_USE_DCACHE
Enable Data Cache
0
C_USE_DIV
Enable Integer Divider
0
C_USE_EXTENDED_FSL_INSTR
Enable Additional FSL Instructions
0
C_USE_EXT_BRK 0
C_USE_EXT_NM_BRK 0
C_USE_FPU
Enable Floating Point Unit
0
C_USE_HW_MUL
Enable Integer Multiplier
1
C_USE_ICACHE
Enable Instruction Cache
0
C_USE_INTERRUPT 0
C_USE_MMU
Memory Management
0
C_USE_MSR_INSTR
Enable Additional Machine Status Register Instructions
1
C_USE_PCMP_INSTR
Enable Pattern Comparator
1
 
MEMORY MAP
D=DATA ADDRESSABLE    I=INSTRUCTION ADDRESSABLE
D I BASE HIGH MODULE
  0x00000000 0x00003FFF C_BASEADDR:C_HIGHADDRdlmb_cntlr
  0x00000000 0x00003FFF C_BASEADDR:C_HIGHADDRilmb_cntlr
0x81400000 0x8140FFFF C_BASEADDR:C_HIGHADDRSwitches_8Bit
0x81420000 0x8142FFFF C_BASEADDR:C_HIGHADDRPush_Buttons_3Bit
0x81440000 0x8144FFFF C_BASEADDR:C_HIGHADDRLEDs_8Bit
0x81460000 0x8146FFFF C_BASEADDR:C_HIGHADDRLED_7SEGMENT
0x84000000 0x8400FFFF C_BASEADDR:C_HIGHADDRRS232_PORT
0x84400000 0x8440FFFF C_BASEADDR:C_HIGHADDRmdm_0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 748 4656 16
Slice Flip Flops 917 9312 9
4 input LUTs 1420 9312 15
IOs 2296 NA NA
bonded IOBs 0 232 0
MULT18X18SIOs 3 20 15




Debuggers TOC

mdm_0   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

IP Specs
Core Version Documentation
mdm 1.00.e IP DRIVER


mdm_0 IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 Debug_SYS_Rst O 1 Debug_SYS_Rst
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
MBDEBUG_0 INITIATOR XIL_MBDEBUG2 microblaze_0_mdm_bus microblaze_0
SPLB SLAVE PLBV46 mb_plb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_BASEADDR
Base Address
0x84400000
C_HIGHADDR
High Address
0x8440FFFF
C_INTERCONNECT
Specifies the Bus Interface for the JTAG UART
1
C_JTAG_CHAIN
Specifies the JTAG user-defined register used
2
C_MB_DBG_PORTS
Number of MicroBlaze debug ports
1
C_OPB_AWIDTH
OPB Address Bus Width
32
C_OPB_DWIDTH
OPB Data Bus Width
32
C_SPLB_AWIDTH
PLB Address Bus Width
32
 
Name Value
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_UART_WIDTH
UART Data size
8
C_USE_UART
Enable JTAG UART
1
C_WRITE_FSL_PORTS
Enable Write FSL Port
0
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 88 4656 1
Slice Flip Flops 119 9312 1
4 input LUTs 142 9312 1
IOs 498 NA NA
bonded IOBs 0 232 0
GCLKs 2 24 8




Busses TOC

dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 1.00.a IP


dlmb IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 LMB_Clk I 1 clk_50_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DLMB
dlmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH
Active High External Reset
1
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 4656 0
Slice Flip Flops 1 9312 0
4 input LUTs 1 9312 0
IOs 211 NA NA
bonded IOBs 0 232 0


ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 1.00.a IP


ilmb IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 LMB_Clk I 1 clk_50_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER ILMB
ilmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_EXT_RESET_HIGH
Active High External Reset
1
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_LMB_NUM_SLAVES
Number of Bus Slaves
1
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 1 4656 0
Slice Flip Flops 1 9312 0
4 input LUTs 1 9312 0
IOs 211 NA NA
bonded IOBs 0 232 0


mb_plb   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.04.a IP


mb_plb IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 PLB_Clk I 1 clk_50_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DPLB
microblaze_0 MASTER IPLB
LEDs_8Bit SLAVE SPLB
LED_7SEGMENT SLAVE SPLB
Push_Buttons_3Bit SLAVE SPLB
Switches_8Bit SLAVE SPLB
RS232_PORT SLAVE SPLB
mdm_0 SLAVE SPLB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_BASEADDR
Base Address
0b1111111111
C_HIGHADDR
High Address
0b0000000000
C_ADDR_PIPELINING_TYPE
Enable Address Pipelining Type
1
C_ARB_TYPE
Selects the Arbitration Scheme
0
C_DCR_AWIDTH
DCR Address Bus Width
10
C_DCR_DWIDTH
DCR Data Bus Width
32
C_DCR_INTFCE
Include DCR Interface and Error Registers
0
C_EXT_RESET_HIGH
External Reset Active High
1
 
Name Value
C_IRQ_ACTIVE
IRQ Active State
1
C_NUM_CLK_PLB2OPB_REARB
<qt>Number of PLB Clock Periods a PLB Master that Received a Rearbitrate from an OPB2PLB Bridge on a Read Operation is Denied Grant on the PLB Bus</qt>
5
C_P2P
Optimize PLB for Point-to-point Topology
0
C_PLBV46_AWIDTH
PLB Address Bus Width
32
C_PLBV46_DWIDTH
PLB Data Bus Width
32
C_PLBV46_MID_WIDTH
PLB Master ID Bus Width
1
C_PLBV46_NUM_MASTERS
Number of PLB Masters
2
C_PLBV46_NUM_SLAVES
Number of PLB Slaves
6
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 255 4656 5
Slice Flip Flops 155 9312 1
4 input LUTs 435 9312 4
IOs 992 NA NA
bonded IOBs 0 232 0




Memorys TOC

lmb_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


lmb_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
PORTA TARGET XIL_BRAM ilmb_port ilmb_cntlr
PORTB TARGET XIL_BRAM dlmb_port dlmb_cntlr


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_MEMSIZE
Size of BRAM(s) in Bytes
0x4000
C_NUM_WE
Number of Byte Write Enables
4
C_PORT_AWIDTH
Address Width of Port A and B
32
C_PORT_DWIDTH
Data Width of Port A and B
32
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 0 4656 0
IOs 206 NA NA
bonded IOBs 0 232 0
BRAMs 8 20 40




Memory Controllers TOC

dlmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 2.10.b IP DRIVER


dlmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
BRAM_PORT INITIATOR XIL_BRAM dlmb_port lmb_bram
SLMB SLAVE LMB dlmb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x00003FFF
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_MASK
LMB Address Decode Mask
0x00800000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 4656 0
Slice Flip Flops 2 9312 0
4 input LUTs 6 9312 0
IOs 209 NA NA
bonded IOBs 0 232 0


ilmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 2.10.b IP DRIVER


ilmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
BRAM_PORT INITIATOR XIL_BRAM ilmb_port lmb_bram
SLMB SLAVE LMB ilmb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR
LMB BRAM Base Address
0x00000000
C_HIGHADDR
LMB BRAM High Address
0x00003FFF
C_LMB_AWIDTH
LMB Address Bus Width
32
C_LMB_DWIDTH
LMB Data Bus Width
32
C_MASK
LMB Address Decode Mask
0x00800000
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 4656 0
Slice Flip Flops 2 9312 0
4 input LUTs 6 9312 0
IOs 209 NA NA
bonded IOBs 0 232 0




Peripherals TOC

LED_7SEGMENT   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP DRIVER


LED_7SEGMENT IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 GPIO_IO_O O 0:11 fpga_0_LED_7SEGMENT_GPIO_IO_O_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
SPLB SLAVE PLBV46 mb_plb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_BASEADDR
Base Address
0x81460000
C_HIGHADDR
High Address
0x8146FFFF
C_ALL_INPUTS
Channel 1 is Input Only
0
C_ALL_INPUTS_2
Channel 2 is Input Only
0
C_DOUT_DEFAULT
Channel 1 Data Out Default Value
0x00000000
C_DOUT_DEFAULT_2
Channel 2 Data Out Default Value
0x00000000
C_GPIO2_WIDTH
GPIO2 Data Channel Width
32
C_GPIO_WIDTH
GPIO Data Channel Width
12
C_INTERRUPT_PRESENT
GPIO Supports Interrupts
0
 
Name Value
C_IS_DUAL
Enable Channel 2
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_TRI_DEFAULT
Channel 1 Tri-state Default Value
0xFFFFFFFF
C_TRI_DEFAULT_2
Channel 2 Tri-state Default Value
0xFFFFFFFF
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 96 4656 2
Slice Flip Flops 155 9312 1
4 input LUTs 84 9312 0
IOs 334 NA NA
bonded IOBs 0 232 0


LEDs_8Bit   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP DRIVER


LEDs_8Bit IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 GPIO_IO_O O 0:7 fpga_0_LEDs_8Bit_GPIO_IO_O_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
SPLB SLAVE PLBV46 mb_plb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_BASEADDR
Base Address
0x81440000
C_HIGHADDR
High Address
0x8144FFFF
C_ALL_INPUTS
Channel 1 is Input Only
0
C_ALL_INPUTS_2
Channel 2 is Input Only
0
C_DOUT_DEFAULT
Channel 1 Data Out Default Value
0x00000000
C_DOUT_DEFAULT_2
Channel 2 Data Out Default Value
0x00000000
C_GPIO2_WIDTH
GPIO2 Data Channel Width
32
C_GPIO_WIDTH
GPIO Data Channel Width
8
C_INTERRUPT_PRESENT
GPIO Supports Interrupts
0
 
Name Value
C_IS_DUAL
Enable Channel 2
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_TRI_DEFAULT
Channel 1 Tri-state Default Value
0xFFFFFFFF
C_TRI_DEFAULT_2
Channel 2 Tri-state Default Value
0xFFFFFFFF
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 79 4656 1
Slice Flip Flops 125 9312 1
4 input LUTs 70 9312 0
IOs 322 NA NA
bonded IOBs 0 232 0


Push_Buttons_3Bit   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP DRIVER


Push_Buttons_3Bit IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 GPIO_IO_I I 0:2 fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
SPLB SLAVE PLBV46 mb_plb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_BASEADDR
Base Address
0x81420000
C_HIGHADDR
High Address
0x8142FFFF
C_ALL_INPUTS
Channel 1 is Input Only
1
C_ALL_INPUTS_2
Channel 2 is Input Only
0
C_DOUT_DEFAULT
Channel 1 Data Out Default Value
0x00000000
C_DOUT_DEFAULT_2
Channel 2 Data Out Default Value
0x00000000
C_GPIO2_WIDTH
GPIO2 Data Channel Width
32
C_GPIO_WIDTH
GPIO Data Channel Width
3
C_INTERRUPT_PRESENT
GPIO Supports Interrupts
0
 
Name Value
C_IS_DUAL
Enable Channel 2
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_TRI_DEFAULT
Channel 1 Tri-state Default Value
0xFFFFFFFF
C_TRI_DEFAULT_2
Channel 2 Tri-state Default Value
0xFFFFFFFF
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 59 4656 1
Slice Flip Flops 90 9312 0
4 input LUTs 55 9312 0
IOs 307 NA NA
bonded IOBs 0 232 0


RS232_PORT   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.01.a IP DRIVER


RS232_PORT IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 RX I 1 fpga_0_RS232_PORT_RX_pin
1 TX O 1 fpga_0_RS232_PORT_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
SPLB SLAVE PLBV46 mb_plb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_BASEADDR
Base Address
0x84000000
C_HIGHADDR
High Address
0x8400FFFF
C_BAUDRATE
UART Lite Baud Rate
9600
C_DATA_BITS
Number of Data Bits in a Serial Frame
8
C_ODD_PARITY
Parity Type
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_CLK_FREQ_HZ
Clock Frequency of PLB Slave
50000000
 
Name Value
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_USE_PARITY
Use Parity
0
 
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 110 4656 2
Slice Flip Flops 146 9312 1
4 input LUTs 134 9312 1
IOs 204 NA NA
bonded IOBs 0 232 0


Switches_8Bit   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP DRIVER


Switches_8Bit IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 GPIO_IO_I I 0:7 fpga_0_Switches_8Bit_GPIO_IO_I_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Point 2 Point
SPLB SLAVE PLBV46 mb_plb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_BASEADDR
Base Address
0x81400000
C_HIGHADDR
High Address
0x8140FFFF
C_ALL_INPUTS
Channel 1 is Input Only
1
C_ALL_INPUTS_2
Channel 2 is Input Only
0
C_DOUT_DEFAULT
Channel 1 Data Out Default Value
0x00000000
C_DOUT_DEFAULT_2
Channel 2 Data Out Default Value
0x00000000
C_GPIO2_WIDTH
GPIO2 Data Channel Width
32
C_GPIO_WIDTH
GPIO Data Channel Width
8
C_INTERRUPT_PRESENT
GPIO Supports Interrupts
0
 
Name Value
C_IS_DUAL
Enable Channel 2
0
C_SPLB_AWIDTH
PLB Address Bus Width
32
C_SPLB_DWIDTH
PLB Data Bus Width
32
C_SPLB_MID_WIDTH
Master ID Bus Width of PLB
1
C_SPLB_NATIVE_DWIDTH
Native Data Bus Width of PLB Slave
32
C_SPLB_NUM_MASTERS
Number of PLB Masters
2
C_SPLB_P2P
PLB Slave Uses P2P Topology
0
C_SPLB_SUPPORT_BURSTS
PLB Slave is Capable of Bursts
0
C_TRI_DEFAULT
Channel 1 Tri-state Default Value
0xFFFFFFFF
C_TRI_DEFAULT_2
Channel 2 Tri-state Default Value
0xFFFFFFFF
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 79 4656 1
Slice Flip Flops 125 9312 1
4 input LUTs 70 9312 0
IOs 322 NA NA
bonded IOBs 0 232 0


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 2.00.a IP


proc_sys_reset_0 IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 Slowest_sync_clk I 1 clk_50_0000MHz
1 Ext_Reset_In I 1 sys_rst_s
2 MB_Debug_Sys_Rst I 1 Debug_SYS_Rst
3 Dcm_locked I 1 Dcm_all_locked
4 MB_Reset O 1 mb_reset
5 Bus_Struct_Reset O 1 sys_bus_reset
6 Peripheral_Reset O 1 sys_periph_reset


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY
Device Family
spartan3e
C_AUX_RESET_HIGH
Auxiliary Reset Active High
1
C_AUX_RST_WIDTH
Number of Clocks Before Input Change is Recognized On The Auxiliary Reset Input
4
C_EXT_RESET_HIGH
External Reset Active High
1
C_EXT_RST_WIDTH
Number of Clocks Before Input Change is Recognized On The External Reset Input
4
C_NUM_BUS_RST
Number of Bus Structure Reset Registered Outputs
1
C_NUM_PERP_RST
Number of Peripheral Reset Registered Outputs
1
C_SUBFAMILY
Device Subfamily
lx
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 41 4656 0
Slice Flip Flops 67 9312 0
4 input LUTs 51 9312 0
IOs 20 NA NA
bonded IOBs 0 232 0




IP TOC

clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 3.00.a IP


clock_generator_0 IP Image h
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB]SIGNAL
0 CLKIN I 1 dcm_clk_s
1 CLKOUT0 O 1 clk_50_0000MHz
2 RST I 1 net_gnd
3 LOCKED O 1 Dcm_all_locked


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY spartan3e
C_CLKFBIN_FREQ 0
C_CLKFBOUT_BUF TRUE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_MODULE NONE
C_CLKFBOUT_PORT NONE
C_CLKIN_FREQ 50000000
C_CLKOUT0_BUF TRUE
C_CLKOUT0_FREQ 50000000
C_CLKOUT0_GROUP NONE
C_CLKOUT0_MODULE NONE
C_CLKOUT0_PHASE 0
C_CLKOUT0_PORT NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_FREQ 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_MODULE NONE
C_CLKOUT10_PHASE 0
C_CLKOUT10_PORT NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_FREQ 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_MODULE NONE
C_CLKOUT11_PHASE 0
C_CLKOUT11_PORT NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_FREQ 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_MODULE NONE
C_CLKOUT12_PHASE 0
C_CLKOUT12_PORT NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_FREQ 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_MODULE NONE
C_CLKOUT13_PHASE 0
C_CLKOUT13_PORT NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_FREQ 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_MODULE NONE
C_CLKOUT14_PHASE 0
C_CLKOUT14_PORT NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_FREQ 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_MODULE NONE
C_CLKOUT15_PHASE 0
C_CLKOUT15_PORT NONE
C_CLKOUT1_BUF TRUE
C_CLKOUT1_FREQ 0
C_CLKOUT1_GROUP NONE
C_CLKOUT1_MODULE NONE
C_CLKOUT1_PHASE 0
C_CLKOUT1_PORT NONE
C_CLKOUT2_BUF TRUE
C_CLKOUT2_FREQ 0
C_CLKOUT2_GROUP NONE
C_CLKOUT2_MODULE NONE
C_CLKOUT2_PHASE 0
C_CLKOUT2_PORT NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_FREQ 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_MODULE NONE
C_CLKOUT3_PHASE 0
C_CLKOUT3_PORT NONE
C_CLKOUT4_BUF TRUE
C_CLKOUT4_FREQ 0
C_CLKOUT4_GROUP NONE
C_CLKOUT4_MODULE NONE
C_CLKOUT4_PHASE 0
C_CLKOUT4_PORT NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_FREQ 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_MODULE NONE
C_CLKOUT5_PHASE 0
C_CLKOUT5_PORT NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_FREQ 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_MODULE NONE
C_CLKOUT6_PHASE 0
C_CLKOUT6_PORT NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_FREQ 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_MODULE NONE
C_CLKOUT7_PHASE 0
C_CLKOUT7_PORT NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_FREQ 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_MODULE NONE
C_CLKOUT8_PHASE 0
C_CLKOUT8_PORT NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_FREQ 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_MODULE NONE
C_CLKOUT9_PHASE 0
C_CLKOUT9_PORT NONE
C_CLK_GEN UPDATE
C_DCM0_CLK0_BUF false
C_DCM0_CLK180_BUF false
C_DCM0_CLK270_BUF false
C_DCM0_CLK2X180_BUF false
C_DCM0_CLK2X_BUF false
C_DCM0_CLK90_BUF false
C_DCM0_CLKDV180_BUF false
C_DCM0_CLKDV_BUF false
C_DCM0_CLKDV_DIVIDE 2.000000
C_DCM0_CLKFB_BUF false
C_DCM0_CLKFB_MODULE NONE
C_DCM0_CLKFB_PORT NONE
C_DCM0_CLKFX180_BUF false
C_DCM0_CLKFX_BUF false
C_DCM0_CLKFX_DIVIDE 1
C_DCM0_CLKFX_MULTIPLY 4
C_DCM0_CLKIN_BUF false
C_DCM0_CLKIN_DIVIDE_BY_2 false
C_DCM0_CLKIN_MODULE NONE
C_DCM0_CLKIN_PERIOD 0.000000
C_DCM0_CLKIN_PORT NONE
C_DCM0_CLKOUT_PHASE_SHIFT NONE
C_DCM0_CLK_FEEDBACK 1X
C_DCM0_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM0_DFS_FREQUENCY_MODE LOW
C_DCM0_DLL_FREQUENCY_MODE LOW
C_DCM0_DSS_MODE NONE
C_DCM0_DUTY_CYCLE_CORRECTION true
C_DCM0_EXT_RESET_HIGH 1
C_DCM0_FAMILY virtex5
C_DCM0_PHASE_SHIFT 0
C_DCM0_RST_MODULE NONE
C_DCM0_STARTUP_WAIT false
C_DCM1_CLK0_BUF false
C_DCM1_CLK180_BUF false
C_DCM1_CLK270_BUF false
C_DCM1_CLK2X180_BUF false
C_DCM1_CLK2X_BUF false
C_DCM1_CLK90_BUF false
C_DCM1_CLKDV180_BUF false
C_DCM1_CLKDV_BUF false
C_DCM1_CLKDV_DIVIDE 2.000000
C_DCM1_CLKFB_BUF false
C_DCM1_CLKFB_MODULE NONE
C_DCM1_CLKFB_PORT NONE
C_DCM1_CLKFX180_BUF false
C_DCM1_CLKFX_BUF false
C_DCM1_CLKFX_DIVIDE 1
C_DCM1_CLKFX_MULTIPLY 4
C_DCM1_CLKIN_BUF false
C_DCM1_CLKIN_DIVIDE_BY_2 false
C_DCM1_CLKIN_MODULE NONE
C_DCM1_CLKIN_PERIOD 0.000000
C_DCM1_CLKIN_PORT NONE
C_DCM1_CLKOUT_PHASE_SHIFT NONE
C_DCM1_CLK_FEEDBACK 1X
C_DCM1_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM1_DFS_FREQUENCY_MODE LOW
C_DCM1_DLL_FREQUENCY_MODE LOW
C_DCM1_DSS_MODE NONE
C_DCM1_DUTY_CYCLE_CORRECTION true
C_DCM1_EXT_RESET_HIGH 1
C_DCM1_FAMILY virtex5
C_DCM1_PHASE_SHIFT 0
 
Name Value
C_DCM1_RST_MODULE NONE
C_DCM1_STARTUP_WAIT false
C_DCM2_CLK0_BUF false
C_DCM2_CLK180_BUF false
C_DCM2_CLK270_BUF false
C_DCM2_CLK2X180_BUF false
C_DCM2_CLK2X_BUF false
C_DCM2_CLK90_BUF false
C_DCM2_CLKDV180_BUF false
C_DCM2_CLKDV_BUF false
C_DCM2_CLKDV_DIVIDE 2.000000
C_DCM2_CLKFB_BUF false
C_DCM2_CLKFB_MODULE NONE
C_DCM2_CLKFB_PORT NONE
C_DCM2_CLKFX180_BUF false
C_DCM2_CLKFX_BUF false
C_DCM2_CLKFX_DIVIDE 1
C_DCM2_CLKFX_MULTIPLY 4
C_DCM2_CLKIN_BUF false
C_DCM2_CLKIN_DIVIDE_BY_2 false
C_DCM2_CLKIN_MODULE NONE
C_DCM2_CLKIN_PERIOD 0.000000
C_DCM2_CLKIN_PORT NONE
C_DCM2_CLKOUT_PHASE_SHIFT NONE
C_DCM2_CLK_FEEDBACK 1X
C_DCM2_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM2_DFS_FREQUENCY_MODE LOW
C_DCM2_DLL_FREQUENCY_MODE LOW
C_DCM2_DSS_MODE NONE
C_DCM2_DUTY_CYCLE_CORRECTION true
C_DCM2_EXT_RESET_HIGH 1
C_DCM2_FAMILY virtex5
C_DCM2_PHASE_SHIFT 0
C_DCM2_RST_MODULE NONE
C_DCM2_STARTUP_WAIT false
C_DCM3_CLK0_BUF false
C_DCM3_CLK180_BUF false
C_DCM3_CLK270_BUF false
C_DCM3_CLK2X180_BUF false
C_DCM3_CLK2X_BUF false
C_DCM3_CLK90_BUF false
C_DCM3_CLKDV180_BUF false
C_DCM3_CLKDV_BUF false
C_DCM3_CLKDV_DIVIDE 2.000000
C_DCM3_CLKFB_BUF false
C_DCM3_CLKFB_MODULE NONE
C_DCM3_CLKFB_PORT NONE
C_DCM3_CLKFX180_BUF false
C_DCM3_CLKFX_BUF false
C_DCM3_CLKFX_DIVIDE 1
C_DCM3_CLKFX_MULTIPLY 4
C_DCM3_CLKIN_BUF false
C_DCM3_CLKIN_DIVIDE_BY_2 false
C_DCM3_CLKIN_MODULE NONE
C_DCM3_CLKIN_PERIOD 0.000000
C_DCM3_CLKIN_PORT NONE
C_DCM3_CLKOUT_PHASE_SHIFT NONE
C_DCM3_CLK_FEEDBACK 1X
C_DCM3_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM3_DFS_FREQUENCY_MODE LOW
C_DCM3_DLL_FREQUENCY_MODE LOW
C_DCM3_DSS_MODE NONE
C_DCM3_DUTY_CYCLE_CORRECTION true
C_DCM3_EXT_RESET_HIGH 1
C_DCM3_FAMILY virtex5
C_DCM3_PHASE_SHIFT 0
C_DCM3_RST_MODULE NONE
C_DCM3_STARTUP_WAIT false
C_EXT_RESET_HIGH 1
C_PLL0_BANDWIDTH OPTIMIZED
C_PLL0_CLKFBIN_MODULE NONE
C_PLL0_CLKFBIN_PORT NONE
C_PLL0_CLKFBOUT_BUF false
C_PLL0_CLKFBOUT_DESKEW_ADJUST NONE
C_PLL0_CLKFBOUT_MULT 1
C_PLL0_CLKFBOUT_PHASE 0.000000
C_PLL0_CLKIN1_BUF false
C_PLL0_CLKIN1_MODULE NONE
C_PLL0_CLKIN1_PERIOD 0.000000
C_PLL0_CLKIN1_PORT NONE
C_PLL0_CLKOUT0_BUF false
C_PLL0_CLKOUT0_DESKEW_ADJUST NONE
C_PLL0_CLKOUT0_DIVIDE 1
C_PLL0_CLKOUT0_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT0_PHASE 0.000000
C_PLL0_CLKOUT1_BUF false
C_PLL0_CLKOUT1_DESKEW_ADJUST NONE
C_PLL0_CLKOUT1_DIVIDE 1
C_PLL0_CLKOUT1_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT1_PHASE 0.000000
C_PLL0_CLKOUT2_BUF false
C_PLL0_CLKOUT2_DESKEW_ADJUST NONE
C_PLL0_CLKOUT2_DIVIDE 1
C_PLL0_CLKOUT2_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT2_PHASE 0.000000
C_PLL0_CLKOUT3_BUF false
C_PLL0_CLKOUT3_DESKEW_ADJUST NONE
C_PLL0_CLKOUT3_DIVIDE 1
C_PLL0_CLKOUT3_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT3_PHASE 0.000000
C_PLL0_CLKOUT4_BUF false
C_PLL0_CLKOUT4_DESKEW_ADJUST NONE
C_PLL0_CLKOUT4_DIVIDE 1
C_PLL0_CLKOUT4_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT4_PHASE 0.000000
C_PLL0_CLKOUT5_BUF false
C_PLL0_CLKOUT5_DESKEW_ADJUST NONE
C_PLL0_CLKOUT5_DIVIDE 1
C_PLL0_CLKOUT5_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT5_PHASE 0.000000
C_PLL0_COMPENSATION SYSTEM_SYNCHRONOUS
C_PLL0_DIVCLK_DIVIDE 1
C_PLL0_EXT_RESET_HIGH 1
C_PLL0_FAMILY virtex5
C_PLL0_REF_JITTER 0.100000
C_PLL0_RESET_ON_LOSS_OF_LOCK false
C_PLL0_RST_DEASSERT_CLK CLKIN1
C_PLL0_RST_MODULE NONE
C_PLL1_BANDWIDTH OPTIMIZED
C_PLL1_CLKFBIN_MODULE NONE
C_PLL1_CLKFBIN_PORT NONE
C_PLL1_CLKFBOUT_BUF false
C_PLL1_CLKFBOUT_DESKEW_ADJUST NONE
C_PLL1_CLKFBOUT_MULT 1
C_PLL1_CLKFBOUT_PHASE 0.000000
C_PLL1_CLKIN1_BUF false
C_PLL1_CLKIN1_MODULE NONE
C_PLL1_CLKIN1_PERIOD 0.000000
C_PLL1_CLKIN1_PORT NONE
C_PLL1_CLKOUT0_BUF false
C_PLL1_CLKOUT0_DESKEW_ADJUST NONE
C_PLL1_CLKOUT0_DIVIDE 1
C_PLL1_CLKOUT0_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT0_PHASE 0.000000
C_PLL1_CLKOUT1_BUF false
C_PLL1_CLKOUT1_DESKEW_ADJUST NONE
C_PLL1_CLKOUT1_DIVIDE 1
C_PLL1_CLKOUT1_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT1_PHASE 0.000000
C_PLL1_CLKOUT2_BUF false
C_PLL1_CLKOUT2_DESKEW_ADJUST NONE
C_PLL1_CLKOUT2_DIVIDE 1
C_PLL1_CLKOUT2_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT2_PHASE 0.000000
C_PLL1_CLKOUT3_BUF false
C_PLL1_CLKOUT3_DESKEW_ADJUST NONE
C_PLL1_CLKOUT3_DIVIDE 1
C_PLL1_CLKOUT3_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT3_PHASE 0.000000
C_PLL1_CLKOUT4_BUF false
C_PLL1_CLKOUT4_DESKEW_ADJUST NONE
C_PLL1_CLKOUT4_DIVIDE 1
C_PLL1_CLKOUT4_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT4_PHASE 0.000000
C_PLL1_CLKOUT5_BUF false
C_PLL1_CLKOUT5_DESKEW_ADJUST NONE
C_PLL1_CLKOUT5_DIVIDE 1
C_PLL1_CLKOUT5_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT5_PHASE 0.000000
C_PLL1_COMPENSATION SYSTEM_SYNCHRONOUS
C_PLL1_DIVCLK_DIVIDE 1
C_PLL1_EXT_RESET_HIGH 1
C_PLL1_FAMILY virtex5
C_PLL1_REF_JITTER 0.100000
C_PLL1_RESET_ON_LOSS_OF_LOCK false
C_PLL1_RST_DEASSERT_CLK CLKIN1
C_PLL1_RST_MODULE NONE
C_SPEEDGRADE -4
Post Synthesis Device Utilization
Resource Type Used Available Percent
Slices 3 4656 0
Slice Flip Flops 5 9312 0
4 input LUTs 2 9312 0
IOs 21 NA NA
bonded IOBs 0 232 0
GCLKs 1 24 4
DCMs 1 4 25




Timing Information TOC


Post Synthesis Clock Limits
These are the post synthesis clock frequencies. The critical frequencies are marked with green.
The values reported here are post synthesis estimates calculated for each individual module. These values will change after place and route is performed on the entire system.
MODULE CLK Port MAX FREQ
microblaze_0 DCACHE_FSL_OUT_CLK 92.621MHz
microblaze_0 DBG_CLK 92.621MHz
microblaze_0 DBG_UPDATE 92.621MHz
mdm_0 mdm_0/update 103.907MHz
mdm_0 SPLB_Clk 103.907MHz
mdm_0 mdm_0/drck_i 103.907MHz
RS232_PORT SPLB_Clk 150.015MHz
mb_plb PLB_Clk 151.837MHz
proc_sys_reset_0 Slowest_sync_clk 198.531MHz
LEDs_8Bit SPLB_Clk 201.086MHz
LED_7SEGMENT SPLB_Clk 201.086MHz
Push_Buttons_3Bit SPLB_Clk 201.086MHz
Switches_8Bit SPLB_Clk 201.086MHz
ilmb LMB_Clk 249.128MHz
dlmb LMB_Clk 249.128MHz
clock_generator_0 CLKIN 249.128MHz