Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedThu Nov 5 15:01:21 2020 os_platformLIN64
product_versionVivado v2020.1 (64-bit) project_id083e67c005794fbb811258de17b51f97
project_iteration1 random_idae3ff47605875caa853e2d43cee63b98
registration_idae3ff47605875caa853e2d43cee63b98 route_designTRUE
target_devicexc7a15t target_familyartix7
target_packagecpg236 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-10750H CPU @ 2.60GHz cpu_speed1622.818 MHz
os_nameKali os_releaseKali GNU/Linux Rolling
system_ram16.000 GB total_processors1

vivado_usage
other_data
tclmode=2
project_data
constraintsetcount=0 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=24 totalsynthesisruns=24

unisim_transformation
post_unisim_transformation
and2b1l=4 bscane2=1 bufg=3 carry4=189
dsp48e1=3 fdce=378 fdpe=143 fdre=5779
fdse=243 gnd=585 ibuf=12 lut1=363
lut2=664 lut3=1084 lut4=835 lut5=1045
lut6=1463 mmcme2_adv=1 muxf7=240 muxf8=66
obuf=28 obuft=8 ramb36e1=19 ramd32=490
rams32=142 srl16e=196 srlc16e=16 srlc32e=267
vcc=472
pre_unisim_transformation
and2b1l=4 bscane2=1 bufg=3 carry4=189
dsp48e1=3 fdce=378 fdpe=143 fdre=5779
fdse=243 gnd=585 ibuf=4 iobuf=8
lut1=363 lut2=664 lut3=1084 lut4=835
lut5=965 lut6=1383 lut6_2=80 mmcme2_adv=1
muxf7=240 muxf8=66 obuf=28 ram32m=71
ram32x1d=32 ramb36e1=19 srl16e=196 srlc16e=16
srlc32e=267 vcc=472

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA iptotal=1 maxhierdepth=0
numblks=36 numhdlrefblks=0 numhierblks=12 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=24 numsysgenblks=0
synth_mode=OOC_per_IP x_iplanguage=VHDL x_iplibrary=BlockDiagram x_ipname=user_15t
x_ipvendor=xilinx.com x_ipversion=1.00.a
MDM/1
c_addr_size=32 c_avoid_primitives=0 c_bscanid=76547328 c_data_size=32
c_dbg_mem_access=0 c_dbg_reg_access=0 c_debug_interface=0 c_ext_trig_reset_value=0xF1234
c_family=artix7 c_interconnect=2 c_jtag_chain=2 c_lmb_protocol=0
c_m_axi_addr_width=32 c_m_axi_data_width=32 c_m_axi_thread_id_width=1 c_m_axis_data_width=32
c_m_axis_id_width=7 c_mb_dbg_ports=1 c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4
c_s_axi_data_width=32 c_trace_async_reset=0 c_trace_clk_freq_hz=200000000 c_trace_clk_out_phase=90
c_trace_data_width=32 c_trace_id=110 c_trace_output=0 c_trace_protocol=1
c_use_bscan=0 c_use_config_reset=0 c_use_cross_trigger=0 c_use_uart=0
core_container=NA iptotal=1 x_ipcorerevision=18 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=mdm x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=3.2
MicroBlaze/1
c_addr_tag_bits=6 c_allow_dcache_wr=1 c_allow_icache_wr=1 c_area_optimized=0
c_async_interrupt=1 c_async_wakeup=3 c_avoid_primitives=0 c_base_vectors=0x0000000000000000
c_branch_target_cache_size=0 c_cache_byte_size=8192 c_d_axi=1 c_d_lmb=1
c_d_lmb_protocol=0 c_daddr_size=32 c_data_size=32 c_dcache_addr_tag=6
c_dcache_always_used=1 c_dcache_baseaddr=0x0000000060000000 c_dcache_byte_size=8192 c_dcache_data_width=0
c_dcache_force_tag_lutram=0 c_dcache_highaddr=0x000000006007ffff c_dcache_line_len=4 c_dcache_use_writeback=0
c_dcache_victims=0 c_debug_counter_width=32 c_debug_enabled=1 c_debug_event_counters=5
c_debug_external_trace=0 c_debug_interface=0 c_debug_latency_counters=1 c_debug_profile_size=0
c_debug_trace_async_reset=0 c_debug_trace_size=8192 c_div_zero_exception=0 c_dynamic_bus_sizing=0
c_ecc_use_ce_exception=0 c_edge_is_positive=1 c_endianness=1 c_family=artix7
c_fault_tolerant=0 c_fpu_exception=0 c_freq=100000000 c_fsl_exception=0
c_fsl_links=0 c_i_axi=0 c_i_lmb=1 c_i_lmb_protocol=0
c_iaddr_size=32 c_icache_always_used=1 c_icache_baseaddr=0x0000000060000000 c_icache_data_width=0
c_icache_force_tag_lutram=0 c_icache_highaddr=0x000000006007ffff c_icache_line_len=8 c_icache_streams=0
c_icache_victims=0 c_ill_opcode_exception=0 c_imprecise_exceptions=0 c_instance=user_15t_microblaze_0_0
c_instr_size=32 c_interconnect=2 c_interrupt_is_edge=0 c_lmb_data_size=32
c_lockstep_master=0 c_lockstep_slave=0 c_m0_axis_data_width=32 c_m10_axis_data_width=32
c_m11_axis_data_width=32 c_m12_axis_data_width=32 c_m13_axis_data_width=32 c_m14_axis_data_width=32
c_m15_axis_data_width=32 c_m1_axis_data_width=32 c_m2_axis_data_width=32 c_m3_axis_data_width=32
c_m4_axis_data_width=32 c_m5_axis_data_width=32 c_m6_axis_data_width=32 c_m7_axis_data_width=32
c_m8_axis_data_width=32 c_m9_axis_data_width=32 c_m_axi_d_bus_exception=1 c_m_axi_dc_addr_width=32
c_m_axi_dc_aruser_width=5 c_m_axi_dc_awuser_width=5 c_m_axi_dc_buser_width=1 c_m_axi_dc_data_width=32
c_m_axi_dc_exclusive_access=0 c_m_axi_dc_ruser_width=1 c_m_axi_dc_thread_id_width=1 c_m_axi_dc_user_value=31
c_m_axi_dc_wuser_width=1 c_m_axi_dp_addr_width=32 c_m_axi_dp_data_width=32 c_m_axi_dp_exclusive_access=0
c_m_axi_dp_thread_id_width=1 c_m_axi_i_bus_exception=0 c_m_axi_ic_addr_width=32 c_m_axi_ic_aruser_width=5
c_m_axi_ic_awuser_width=5 c_m_axi_ic_buser_width=1 c_m_axi_ic_data_width=32 c_m_axi_ic_ruser_width=1
c_m_axi_ic_thread_id_width=1 c_m_axi_ic_user_value=31 c_m_axi_ic_wuser_width=1 c_m_axi_ip_addr_width=32
c_m_axi_ip_data_width=32 c_m_axi_ip_thread_id_width=1 c_mmu_dtlb_size=4 c_mmu_itlb_size=2
c_mmu_privileged_instr=0 c_mmu_tlb_access=3 c_mmu_zones=2 c_num_sync_ff_clk=2
c_num_sync_ff_clk_debug=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_dbg_clk=1 c_num_sync_ff_dbg_trace_clk=2
c_number_of_pc_brk=2 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0 c_opcode_0x0_illegal=0
c_optimization=0 c_pc_width=32 c_piaddr_size=32 c_pvr=0
c_pvr_user1=0x00 c_pvr_user2=0x00000000 c_reset_msr=0x00000000 c_s0_axis_data_width=32
c_s10_axis_data_width=32 c_s11_axis_data_width=32 c_s12_axis_data_width=32 c_s13_axis_data_width=32
c_s14_axis_data_width=32 c_s15_axis_data_width=32 c_s1_axis_data_width=32 c_s2_axis_data_width=32
c_s3_axis_data_width=32 c_s4_axis_data_width=32 c_s5_axis_data_width=32 c_s6_axis_data_width=32
c_s7_axis_data_width=32 c_s8_axis_data_width=32 c_s9_axis_data_width=32 c_sco=0
c_unaligned_exceptions=0 c_use_barrel=1 c_use_branch_target_cache=0 c_use_config_reset=0
c_use_dcache=1 c_use_div=0 c_use_ext_brk=0 c_use_ext_nm_brk=0
c_use_extended_fsl_instr=0 c_use_fpu=0 c_use_hw_mul=1 c_use_icache=1
c_use_interrupt=1 c_use_mmu=0 c_use_msr_instr=1 c_use_non_secure=0
c_use_pcmp_instr=1 c_use_reorder_instr=1 c_use_stack_protection=0 core_container=NA
g_template_list=6 iptotal=1 x_ipcorerevision=3 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=microblaze x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=11.0
axi_crossbar_v2_1_22_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=0 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=1 c_family=artix7
c_m_axi_addr_width=0x00000013 c_m_axi_base_addr=0x0000000060000000 c_m_axi_read_connectivity=0x00000003 c_m_axi_read_issuing=0x00000002
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0x00000001 c_m_axi_write_issuing=0x00000020 c_num_addr_ranges=1
c_num_master_slots=1 c_num_slave_slots=2 c_r_register=0 c_s_axi_arb_priority=0x0000000000000000
c_s_axi_base_id=0x0000000100000000 c_s_axi_read_acceptance=0x0000000200000002 c_s_axi_single_thread=0x0000000000000000 c_s_axi_thread_id_width=0x0000000000000000
c_s_axi_write_acceptance=0x0000000200000020 core_container=NA iptotal=1 x_ipcorerevision=22
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_crossbar_v2_1_22_axi_crossbar/2
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=artix7
c_m_axi_addr_width=0x0000001000000010000000100000001000000010 c_m_axi_base_addr=0x00000000412000000000000041c00000000000004060000000000000400100000000000040000000 c_m_axi_read_connectivity=0x0000000100000001000000010000000100000001 c_m_axi_read_issuing=0x0000000100000001000000010000000100000001
c_m_axi_secure=0x0000000000000000000000000000000000000000 c_m_axi_write_connectivity=0x0000000100000001000000010000000100000001 c_m_axi_write_issuing=0x0000000100000001000000010000000100000001 c_num_addr_ranges=1
c_num_master_slots=5 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=22
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_data_fifo_v2_1_20_axi_data_fifo/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=0 c_axi_read_fifo_delay=1
c_axi_read_fifo_depth=512 c_axi_read_fifo_type=bram c_axi_ruser_width=1 c_axi_supports_user_signals=0
c_axi_write_fifo_delay=1 c_axi_write_fifo_depth=512 c_axi_write_fifo_type=bram c_axi_wuser_width=1
c_family=artix7 core_container=NA iptotal=1 x_ipcorerevision=20
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_data_fifo x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_data_fifo_v2_1_20_axi_data_fifo/2
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=0 c_axi_read_fifo_delay=1
c_axi_read_fifo_depth=512 c_axi_read_fifo_type=bram c_axi_ruser_width=1 c_axi_supports_user_signals=0
c_axi_write_fifo_delay=1 c_axi_write_fifo_depth=512 c_axi_write_fifo_type=bram c_axi_wuser_width=1
c_family=artix7 core_container=NA iptotal=1 x_ipcorerevision=20
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_data_fifo x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_data_fifo_v2_1_20_axi_data_fifo/3
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=0 c_axi_read_fifo_delay=1
c_axi_read_fifo_depth=512 c_axi_read_fifo_type=bram c_axi_ruser_width=1 c_axi_supports_user_signals=0
c_axi_write_fifo_delay=0 c_axi_write_fifo_depth=0 c_axi_write_fifo_type=lut c_axi_wuser_width=1
c_family=artix7 core_container=NA iptotal=1 x_ipcorerevision=20
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_data_fifo x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_emc/1
c_axi_clk_period_ps=10000 c_family=artix7 c_include_datawidth_matching_0=1 c_include_datawidth_matching_1=1
c_include_datawidth_matching_2=1 c_include_datawidth_matching_3=1 c_include_negedge_ioregs=0 c_instance=axi_emc_inst
c_lflash_period_ps=10000 c_linear_flash_sync_burst=0 c_max_mem_width=8 c_mem0_type=1
c_mem0_width=8 c_mem1_type=0 c_mem1_width=16 c_mem2_type=0
c_mem2_width=16 c_mem3_type=0 c_mem3_width=16 c_mem_a_lsb=0
c_mem_a_msb=31 c_num_banks_mem=1 c_page_size=16 c_parity_type_mem_0=0
c_parity_type_mem_1=0 c_parity_type_mem_2=0 c_parity_type_mem_3=0 c_port_diff=0
c_s_axi_en_reg=0 c_s_axi_mem0_baseaddr=0x60000000 c_s_axi_mem0_highaddr=0x6007FFFF c_s_axi_mem1_baseaddr=0xB0000000
c_s_axi_mem1_highaddr=0xBFFFFFFF c_s_axi_mem2_baseaddr=0xC0000000 c_s_axi_mem2_highaddr=0xCFFFFFFF c_s_axi_mem3_baseaddr=0xD0000000
c_s_axi_mem3_highaddr=0xDFFFFFFF c_s_axi_mem_addr_width=32 c_s_axi_mem_data_width=32 c_s_axi_mem_id_width=1
c_s_axi_reg_addr_width=5 c_s_axi_reg_data_width=32 c_synch_pipedelay_0=1 c_synch_pipedelay_1=1
c_synch_pipedelay_2=1 c_synch_pipedelay_3=1 c_tavdv_ps_mem_0=8000 c_tavdv_ps_mem_1=15000
c_tavdv_ps_mem_2=15000 c_tavdv_ps_mem_3=15000 c_tcedv_ps_mem_0=8000 c_tcedv_ps_mem_1=15000
c_tcedv_ps_mem_2=15000 c_tcedv_ps_mem_3=15000 c_thzce_ps_mem_0=8000 c_thzce_ps_mem_1=7000
c_thzce_ps_mem_2=7000 c_thzce_ps_mem_3=7000 c_thzoe_ps_mem_0=8000 c_thzoe_ps_mem_1=7000
c_thzoe_ps_mem_2=7000 c_thzoe_ps_mem_3=7000 c_tlzwe_ps_mem_0=3000 c_tlzwe_ps_mem_1=0
c_tlzwe_ps_mem_2=0 c_tlzwe_ps_mem_3=0 c_tpacc_ps_flash_0=25000 c_tpacc_ps_flash_1=25000
c_tpacc_ps_flash_2=25000 c_tpacc_ps_flash_3=25000 c_twc_ps_mem_0=8000 c_twc_ps_mem_1=15000
c_twc_ps_mem_2=15000 c_twc_ps_mem_3=15000 c_twp_ps_mem_0=8000 c_twp_ps_mem_1=12000
c_twp_ps_mem_2=12000 c_twp_ps_mem_3=12000 c_twph_ps_mem_0=12000 c_twph_ps_mem_1=12000
c_twph_ps_mem_2=12000 c_twph_ps_mem_3=12000 c_use_startup=0 c_wr_rec_time_mem_0=27000
c_wr_rec_time_mem_1=27000 c_wr_rec_time_mem_2=27000 c_wr_rec_time_mem_3=27000 core_container=NA
iptotal=1 x_ipcorerevision=21 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=axi_emc x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=3.0
axi_gpio/1
c_all_inputs=0 c_all_inputs_2=1 c_all_outputs=1 c_all_outputs_2=0
c_dout_default=0x00000000 c_dout_default_2=0x00000000 c_family=artix7 c_gpio2_width=1
c_gpio_width=2 c_interrupt_present=1 c_is_dual=1 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=23 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_gpio/2
c_all_inputs=0 c_all_inputs_2=0 c_all_outputs=1 c_all_outputs_2=0
c_dout_default=0x00000007 c_dout_default_2=0x00000000 c_family=artix7 c_gpio2_width=32
c_gpio_width=3 c_interrupt_present=0 c_is_dual=0 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=23 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_intc/1
c_addr_width=32 c_async_intr=0xFFFFFFFC c_cascade_master=0 c_disable_synchronizers=0
c_en_cascade_mode=0 c_enable_async=0 c_family=artix7 c_has_cie=1
c_has_fast=0 c_has_ilr=0 c_has_ipr=1 c_has_ivr=1
c_has_sie=1 c_instance=user_15t_axi_intc_0_0 c_irq_active=0x1 c_irq_is_level=1
c_ivar_reset_value=0x0000000000000010 c_kind_of_edge=0xFFFFFFFF c_kind_of_intr=0xfffffffc c_kind_of_lvl=0xFFFFFFFF
c_mb_clk_not_connected=1 c_num_intr_inputs=2 c_num_sw_intr=0 c_num_sync_ff=2
c_s_axi_addr_width=9 c_s_axi_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=14 x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_intc
x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=4.1
axi_register_slice_v2_1_21_axi_register_slice/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=0 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_family=artix7 c_num_slr_crossings=0
c_pipelines_master_ar=0 c_pipelines_master_aw=0 c_pipelines_master_b=0 c_pipelines_master_r=0
c_pipelines_master_w=0 c_pipelines_middle_ar=0 c_pipelines_middle_aw=0 c_pipelines_middle_b=0
c_pipelines_middle_r=0 c_pipelines_middle_w=0 c_pipelines_slave_ar=0 c_pipelines_slave_aw=0
c_pipelines_slave_b=0 c_pipelines_slave_r=0 c_pipelines_slave_w=0 c_reg_config_ar=7
c_reg_config_aw=7 c_reg_config_b=7 c_reg_config_r=1 c_reg_config_w=1
c_reserve_mode=0 core_container=NA iptotal=1 x_ipcorerevision=21
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_register_slice x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_register_slice_v2_1_21_axi_register_slice/2
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=0 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_family=artix7 c_num_slr_crossings=0
c_pipelines_master_ar=0 c_pipelines_master_aw=0 c_pipelines_master_b=0 c_pipelines_master_r=0
c_pipelines_master_w=0 c_pipelines_middle_ar=0 c_pipelines_middle_aw=0 c_pipelines_middle_b=0
c_pipelines_middle_r=0 c_pipelines_middle_w=0 c_pipelines_slave_ar=0 c_pipelines_slave_aw=0
c_pipelines_slave_b=0 c_pipelines_slave_r=0 c_pipelines_slave_w=0 c_reg_config_ar=7
c_reg_config_aw=7 c_reg_config_b=7 c_reg_config_r=1 c_reg_config_w=1
c_reserve_mode=0 core_container=NA iptotal=1 x_ipcorerevision=21
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_register_slice x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_register_slice_v2_1_21_axi_register_slice/3
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=0 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_family=artix7 c_num_slr_crossings=0
c_pipelines_master_ar=0 c_pipelines_master_aw=0 c_pipelines_master_b=0 c_pipelines_master_r=0
c_pipelines_master_w=0 c_pipelines_middle_ar=0 c_pipelines_middle_aw=0 c_pipelines_middle_b=0
c_pipelines_middle_r=0 c_pipelines_middle_w=0 c_pipelines_slave_ar=0 c_pipelines_slave_aw=0
c_pipelines_slave_b=0 c_pipelines_slave_r=0 c_pipelines_slave_w=0 c_reg_config_ar=7
c_reg_config_aw=0 c_reg_config_b=0 c_reg_config_r=1 c_reg_config_w=0
c_reserve_mode=0 core_container=NA iptotal=1 x_ipcorerevision=21
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_register_slice x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_timer/1
c_count_width=32 c_family=artix7 c_gen0_assert=1 c_gen1_assert=1
c_one_timer_only=0 c_s_axi_addr_width=5 c_s_axi_data_width=32 c_trig0_assert=1
c_trig1_assert=1 core_container=NA iptotal=1 x_ipcorerevision=23
x_iplanguage=VHDL x_iplibrary=ip x_ipname=axi_timer x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.0
axi_uartlite/1
c_baudrate=9600 c_data_bits=8 c_family=artix7 c_odd_parity=0
c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=25 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
blk_mem_gen_v8_4_4/1
c_addra_width=32 c_addrb_width=32 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=8 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=1 c_est_power_summary=Estimated Power for IP _ 20.388 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=1
c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=user_15t_lmb_bram_0.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=8192 c_read_depth_b=8192 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=32 c_read_width_b=32 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=1
c_use_byte_wea=1 c_use_byte_web=1 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=4 c_web_width=4
c_write_depth_a=8192 c_write_depth_b=8192 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=32 c_write_width_b=32 c_xdevicefamily=artix7 core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
clk_wiz_v6_0_5_0_0/1
clkin1_period=83.333 clkin2_period=10.0 clock_mgr_type=NA component_name=user_15t_clk_wiz_0_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
lmb_bram_if_cntlr/1
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000007FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_protocol=0 c_mask=0x0000000040000000
c_mask1=0x0000000000800000 c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2
core_container=NA iptotal=1 x_ipcorerevision=18 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=4.0
lmb_bram_if_cntlr/2
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000007FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_protocol=0 c_mask=0x0000000020000000
c_mask1=0x0000000000800000 c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2
core_container=NA iptotal=1 x_ipcorerevision=18 x_iplanguage=VHDL
x_iplibrary=ip x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=4.0
lmb_v10/1
c_ext_reset_high=1 c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_num_slaves=1
c_lmb_protocol=0 core_container=NA iptotal=2 x_ipcorerevision=11
x_iplanguage=VHDL x_iplibrary=ip x_ipname=lmb_v10 x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=1 c_ext_rst_width=4
c_family=artix7 c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=13
x_iplanguage=VHDL x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2020.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
xlconcat_v2_1_3_xlconcat/1
core_container=NA dout_width=2 in0_width=1 in10_width=1
in11_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in1_width=1 in20_width=1 in21_width=1
in22_width=1 in23_width=1 in24_width=1 in25_width=1
in26_width=1 in27_width=1 in28_width=1 in29_width=1
in2_width=1 in30_width=1 in31_width=1 in3_width=1
in4_width=1 in5_width=1 in6_width=1 in7_width=1
in8_width=1 in9_width=1 iptotal=1 num_ports=2
x_ipcorerevision=3 x_iplanguage=VHDL x_iplibrary=ip x_ipname=xlconcat
x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
xpm_cdc_async_rst/1
core_container=NA def_val=1'b0 dest_sync_ff=2 init_sync_ff=0
inv_def_val=1'b1 iptotal=13 rst_active_high=1 version=0
xpm_cdc_sync_rst/1
core_container=NA def_val=1'b1 dest_sync_ff=5 init=1
init_sync_ff=0 iptotal=5 sim_assert_chk=0 version=0

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 dpip-1=4 dpop-1=1 dpop-2=1
rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=1 pdrc-190=1 timing-9=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.027703 clocks=0.022520
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.073040 die=xc7a15tcpg236-1 dsp=0.001623 dsp_output_toggle=12.500000
dynamic=0.208609 effective_thetaja=5.00 enable_probability=0.990000 family=artix7
ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile) i/o=0.026662
input_toggle=12.500000 junction_temp=26.4 (C) logic=0.009801 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.104123
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.281648 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=cpg236 pct_clock_constrained=4.840000
pct_inputs_defined=8 platform=lin64 process=typical ram_enable=50.000000
ram_write=50.000000 read_saif=False set/reset_probability=0.000000 signal_rate=False
signals=0.016176 simulation_file=None speedgrade=-1 static_prob=False
temp_grade=commercial thetajb=7.5 (C/W) thetasa=4.6 (C/W) toggle_rate=False
user_board_temp=25.0 (C) user_effective_thetaja=5.00 user_junc_temp=26.4 (C) user_thetajb=7.5 (C/W)
user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000
vccadc_voltage=1.800000 vccaux_dynamic_current=0.058636 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000
vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.012643 vccaux_total_current=0.071279
vccaux_voltage=1.800000 vccbram_dynamic_current=0.001875 vccbram_static_current=0.000622 vccbram_total_current=0.002498
vccbram_voltage=1.000000 vccint_dynamic_current=0.077739 vccint_static_current=0.010360 vccint_total_current=0.088099
vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000
vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000
vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000
vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000
vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000
vcco25_voltage=2.500000 vcco33_dynamic_current=0.007106 vcco33_static_current=0.001000 vcco33_total_current=0.008106
vcco33_voltage=3.300000 version=2020.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=4 bufgctrl_util_percentage=12.50
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=20.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=3 dsps_available=45 dsps_fixed=0 dsps_used=3
dsps_util_percentage=6.67
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=25 block_ram_tile_fixed=0 block_ram_tile_used=19 block_ram_tile_util_percentage=76.00
ramb18_available=50 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=25 ramb36_fifo_fixed=0 ramb36_fifo_used=19 ramb36_fifo_util_percentage=76.00
ramb36e1_only_used=19
primitives
and2b1l_functional_category=Others and2b1l_used=4 bscane2_functional_category=Others bscane2_used=1
bufg_functional_category=Clock bufg_used=4 carry4_functional_category=CarryLogic carry4_used=189
dsp48e1_functional_category=Block Arithmetic dsp48e1_used=3 fdce_functional_category=Flop & Latch fdce_used=374
fdpe_functional_category=Flop & Latch fdpe_used=115 fdre_functional_category=Flop & Latch fdre_used=4494
fdse_functional_category=Flop & Latch fdse_used=234 ibuf_functional_category=IO ibuf_used=12
lut1_functional_category=LUT lut1_used=226 lut2_functional_category=LUT lut2_used=659
lut3_functional_category=LUT lut3_used=1021 lut4_functional_category=LUT lut4_used=814
lut5_functional_category=LUT lut5_used=1000 lut6_functional_category=LUT lut6_used=1424
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=240
muxf8_functional_category=MuxFx muxf8_used=66 obuf_functional_category=IO obuf_used=28
obuft_functional_category=IO obuft_used=8 ramb36e1_functional_category=Block Memory ramb36e1_used=19
ramd32_functional_category=Distributed Memory ramd32_used=412 rams32_functional_category=Distributed Memory rams32_used=116
srl16e_functional_category=Distributed Memory srl16e_used=194 srlc16e_functional_category=Distributed Memory srlc16e_used=14
srlc32e_functional_category=Distributed Memory srlc32e_used=265
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=240 f7_muxes_util_percentage=1.47
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=66 f8_muxes_util_percentage=0.81
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=264 lut_as_logic_available=10400 lut_as_logic_fixed=0
lut_as_logic_used=4273 lut_as_logic_util_percentage=41.09 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=661 lut_as_memory_util_percentage=6.89 lut_as_shift_register_fixed=0 lut_as_shift_register_used=397
register_as_and_or_available=20800 register_as_and_or_fixed=0 register_as_and_or_used=4 register_as_and_or_util_percentage=0.02
register_as_flip_flop_available=20800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=5171 register_as_flip_flop_util_percentage=24.86
register_as_latch_available=20800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=10400 slice_luts_fixed=0 slice_luts_used=4934 slice_luts_util_percentage=47.44
slice_registers_available=20800 slice_registers_fixed=0 slice_registers_used=5175 slice_registers_util_percentage=24.88
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=264 lut_as_logic_available=10400 lut_as_logic_fixed=0
lut_as_logic_used=4273 lut_as_logic_util_percentage=41.09 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=661 lut_as_memory_util_percentage=6.89 lut_as_shift_register_fixed=0 lut_as_shift_register_used=397
lut_in_front_of_the_register_is_unused_fixed=397 lut_in_front_of_the_register_is_unused_used=1790 lut_in_front_of_the_register_is_used_fixed=1790 lut_in_front_of_the_register_is_used_used=920
register_driven_from_outside_the_slice_fixed=920 register_driven_from_outside_the_slice_used=2710 register_driven_from_within_the_slice_fixed=2710 register_driven_from_within_the_slice_used=2465
slice_available=8150 slice_fixed=0 slice_registers_available=20800 slice_registers_fixed=0
slice_registers_used=5175 slice_registers_util_percentage=24.88 slice_used=1959 slice_util_percentage=24.04
slicel_fixed=0 slicel_used=1323 slicem_fixed=0 slicem_used=636
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=267 unique_control_sets_util_percentage=3.28
using_o5_and_o6_fixed=3.28 using_o5_and_o6_used=76 using_o5_output_only_fixed=76 using_o5_output_only_used=10
using_o6_output_only_fixed=10 using_o6_output_only_used=311
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=RuntimeOptimized -fanout_limit=default::10000
-flatten_hierarchy=none -fsm_extraction=off -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7a15tcpg236-1 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=user_15t_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:18s hls_ip=0 memory_gain=231.375MB memory_peak=2349.887MB