Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedMon Jul 20 15:04:04 2020 os_platformWIN64
product_versionVivado v2020.1 (64-bit) project_idaa71c6191e634f719a406a30273b1849
project_iteration1 random_id5b49ccb978975b6eb46b0d9e2bb5424c
registration_id5b49ccb978975b6eb46b0d9e2bb5424c route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Xeon(R) CPU E5-1650 v2 @ 3.50GHz cpu_speed3492 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
commandsinput_type_tcl_command_here=3 filesetpanel_file_set_panel_tree=1 flownavigatortreepanel_flow_navigator_tree=1
java_command_handlers
runbitgen=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=1 carry4=21 fdre=49 gnd=2
ibuf=7 lut1=4 lut2=42 lut3=2
lut4=16 lut6=2 obuf=10 vcc=1
xadc=1
pre_unisim_transformation
bufg=1 carry4=21 fdre=49 gnd=2
ibuf=7 lut1=4 lut2=42 lut3=2
lut4=16 lut6=2 obuf=10 vcc=1
xadc=1

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

ip_statistics
xadc_wiz_v3_3_8/1
channel_averaging=None component_name=xadc_wiz_0 core_container=false dclk_frequency=125
enable_axi=false enable_axi4stream=false enable_busy=true enable_convst=false
enable_convstclk=false enable_dclk=true enable_drp=true enable_eoc=true
enable_eos=true enable_vbram_alaram=false enable_vccaux_alaram=false enable_vccddro_alaram=false
enable_vccint_alaram=false enable_vccpaux_alaram=false enable_vccpint_alaram=false iptotal=1
ot_alaram=false sequencer_mode=on startup_channel_selection=contineous_sequence timing_mode=continuous
user_temp_alaram=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-17=17 timing-18=12

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") clocks=0.001103 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.106003
die=xc7z020clg400-1 dsp_output_toggle=12.500000 dynamic=0.009675 effective_thetaja=11.53
enable_probability=0.990000 family=zynq ff_toggle=12.500000 flow_state=routed
heatsink=none i/o=0.005688 input_toggle=12.500000 junction_temp=26.3 (C)
logic=0.000214 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.115678
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=clg400
pct_clock_constrained=0.000000 pct_inputs_defined=14 platform=nt64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.000245 simulation_file=None speedgrade=-1
static_prob=False temp_grade=commercial thetajb=7.4 (C/W) thetasa=0.0 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.53 user_junc_temp=26.3 (C)
user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.001000 vccadc_static_current=0.020000
vccadc_total_current=0.021000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000204 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.010264
vccaux_total_current=0.010468 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000441
vccbram_total_current=0.000441 vccbram_voltage=1.000000 vccint_dynamic_current=0.002297 vccint_static_current=0.007443
vccint_total_current=0.009741 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.001579 vcco33_static_current=0.001000
vcco33_total_current=0.002579 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000
vcco_ddr_total_current=0.000000 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000
vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000
vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.010330
vccpaux_total_current=0.010330 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000 vccpint_static_current=0.016350
vccpint_total_current=0.016350 vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000 vccpll_static_current=0.003000
vccpll_total_current=0.003000 vccpll_voltage=1.800000 version=2020.1 xadc=0.002425

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 carry4_functional_category=CarryLogic carry4_used=21
fdre_functional_category=Flop & Latch fdre_used=49 ibuf_functional_category=IO ibuf_used=7
lut1_functional_category=LUT lut1_used=4 lut2_functional_category=LUT lut2_used=42
lut3_functional_category=LUT lut3_used=2 lut4_functional_category=LUT lut4_used=16
lut6_functional_category=LUT lut6_used=2 obuf_functional_category=IO obuf_used=10
xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=51 lut_as_logic_util_percentage=0.10
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=49 register_as_flip_flop_util_percentage=0.05
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=51 slice_luts_util_percentage=0.10
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=49 slice_registers_util_percentage=0.05
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=51 lut_as_logic_util_percentage=0.10 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=16 lut_in_front_of_the_register_is_used_fixed=16 lut_in_front_of_the_register_is_used_used=0
register_driven_from_outside_the_slice_fixed=0 register_driven_from_outside_the_slice_used=16 register_driven_from_within_the_slice_fixed=16 register_driven_from_within_the_slice_used=33
slice_available=13300 slice_fixed=0 slice_registers_available=106400 slice_registers_fixed=0
slice_registers_used=49 slice_registers_util_percentage=0.05 slice_used=27 slice_util_percentage=0.20
slicel_fixed=0 slicel_used=21 slicem_fixed=0 slicem_used=6
unique_control_sets_available=13300 unique_control_sets_fixed=13300 unique_control_sets_used=4 unique_control_sets_util_percentage=0.03
using_o5_and_o6_fixed=0.03 using_o5_and_o6_used=15 using_o5_output_only_fixed=15 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=36
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=1 xadc_used=1 xadc_util_percentage=100.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=RuntimeOptimized -fanout_limit=default::10000
-flatten_hierarchy=none -fsm_extraction=off -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7z020clg400-1 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=XADCdemo -verilog_define=default::[not_specified]
usage
elapsed=00:00:40s hls_ip=0 memory_gain=189.203MB memory_peak=1275.090MB