Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version3247384
date_generatedTue Jul 26 11:43:25 2022 os_platformWIN64
product_versionVivado v2021.1 (64-bit) project_ida619354807cd4babbfc88eb78959c61f
project_iteration1 random_id98411614e97456ac81b93e31d34e0e7c
registration_id98411614e97456ac81b93e31d34e0e7c route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Xeon(R) Gold 6136 CPU @ 3.00GHz cpu_speed2993 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram343.000 GB total_processors2

vivado_usage
gui_handlers
basedialog_ok=1 basedialog_yes=1 commandsinput_type_tcl_command_here=1 flownavigatortreepanel_flow_navigator_tree=1
java_command_handlers
runbitgen=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=37 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=6 bufh=1 carry4=593 dsp48e1=4
fdce=76 fdpe=77 fdre=5161 fdse=124
gnd=230 ibuf=29 ibuf_intermdisable=16 ibufds_intermdisable_int=4
idelayctrl=1 idelaye2=16 in_fifo=2 inv=3
iserdese2=16 lut1=638 lut2=1543 lut3=1101
lut4=1434 lut5=1549 lut6=3183 mmcme2_adv=1
muxf7=271 muxf8=53 obuf=80 obufds=2
obuft=23 obuftds=4 oddr=5 oserdese2=42
out_fifo=4 phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1
phy_control=1 plle2_adv=2 ramb18e1=1 ramb36e1=32
ramd32=570 rams32=186 srl16e=41 srlc32e=13
vcc=177 xadc=1
pre_unisim_transformation
bufg=6 bufh=1 carry4=593 dsp48e1=4
fdce=76 fdpe=77 fdre=5161 fdse=124
gnd=230 ibuf=25 idelayctrl=1 idelaye2=16
in_fifo=2 iobuf=4 iobuf_intermdisable=16 iobufds_intermdisable=2
iserdese2=16 lut1=638 lut2=1543 lut3=1101
lut4=1434 lut5=1549 lut6=3183 mmcme2_adv=1
muxf7=271 muxf8=53 obuf=80 obufds=1
obuft=3 oddr=5 oserdese2=42 out_fifo=4
phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1 phy_control=1
plle2_adv=2 ram32m=93 ram32x1d=6 ramb18e1=1
ramb36e1=32 srl16e=41 srlc32e=13 vcc=177
xadc=1

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=32 bram_ports_newly_gated=0 bram_ports_total=66 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=5386 srls_augmented=0
srls_newly_gated=0 srls_total=54

ip_statistics
blk_mem_gen_v8_4_4/1
c_addra_width=17 c_addrb_width=17 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=32 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 8.861424 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=BRAM_1.mem
c_init_file_name=[user-defined] c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=1 c_mem_type=3 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=93800 c_read_depth_b=93800 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=12 c_read_width_b=12 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=1 c_web_width=1
c_write_depth_a=93800 c_write_depth_b=93800 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=12 c_write_width_b=12 c_xdevicefamily=artix7 core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VHDL x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
clk_wiz_v6_0_8_0_0/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=NA component_name=ClkGen
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=2 primitive=PLL
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true
cordic_v6_0_17/1
c_architecture=2 c_coarse_rotate=0 c_cordic_function=6 c_data_format=2
c_has_aclk=1 c_has_aclken=0 c_has_aresetn=0 c_has_s_axis_cartesian=1
c_has_s_axis_cartesian_tlast=0 c_has_s_axis_cartesian_tuser=0 c_has_s_axis_phase=0 c_has_s_axis_phase_tlast=0
c_has_s_axis_phase_tuser=0 c_input_width=26 c_iterations=0 c_m_axis_dout_tdata_width=16
c_m_axis_dout_tuser_width=1 c_output_width=14 c_phase_format=0 c_pipeline_mode=-2
c_precision=0 c_round_mode=0 c_s_axis_cartesian_tdata_width=32 c_s_axis_cartesian_tuser_width=1
c_s_axis_phase_tdata_width=32 c_s_axis_phase_tuser_width=1 c_scale_comp=0 c_throttle_scheme=3
c_tlast_resolution=0 c_xdevicefamily=artix7 core_container=false iptotal=1
x_ipcorerevision=17 x_iplanguage=VHDL x_iplibrary=ip x_ipname=cordic
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=6.0
mig_7series_v4_2/1
axi_enable=0 burst_mode=8 burst_type=SEQ clk_period=3333
clkin_period=4999 core_container=NA data_mask=1 debug_port=OFF
dq_width=16 ecc=OFF interface_type=DDR2 internal_vref=1
iptotal=1 language=Verilog level=CONTROLLER memory_address_map=BANK_ROW_COLUMN
memory_part=mt47h64m16hr-25e memory_type=COMP no_of_controllers=1 ordering=STRICT
output_drv=HIGH phy_ratio=4 refclk_freq=200 refclk_type=USE_SYSTEM_CLOCK
rtt_nom=50 synthesis_tool=Vivado sysclk_type=NO_BUFFER use_cs_port=1
use_odt_port=1 vccaux_io=1.8V

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clocks=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=default::[not_specified] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=default::[not_specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_congestion_level=default::5 -min_level=default::[not_specified] -name=default::[not_specified]
-no_header=default::[not_specified] -of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=[specified]
-quiet=default::[not_specified] -return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified]
-routes=default::[not_specified] -setup=default::[not_specified] -show_all_congestion_windows=default::false -suggestion=default::[not_specified]
-timing=default::[not_specified] -verbose=default::[not_specified]
usage
runtime=1.68 secs
usage_count
qor_summary=4

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 dpop-2=4 reqp-1709=1 rpbf-3=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -merge_exceptions =default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified]
-return_string=default::[not_specified] -slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
hpdr-1=1 lutar-1=2 pdrc-190=12 reqp-1959=16
synth-6=1 synth-9=12 timing-10=1 xdcb-5=2

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.007231 clocks=0.030364
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.109735 die=xc7a100tcsg324-1 dsp=0.001133 dsp_output_toggle=12.500000
dynamic=1.081732 effective_thetaja=4.56 enable_probability=0.990000 family=artix7
ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile) i/o=0.559587
input_toggle=12.500000 junction_temp=30.4 (C) logic=0.012853 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.111832
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=1.191466 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=csg324 pct_clock_constrained=13.000000
pct_inputs_defined=2 phaser=0.102361 platform=nt64 pll=0.240195
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.014087 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=5.7 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.56
user_junc_temp=30.4 (C) user_thetajb=5.7 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000862
vccadc_static_current=0.020000 vccadc_total_current=0.020862 vccadc_voltage=1.800000 vccaux_dynamic_current=0.283904
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.018420 vccaux_total_current=0.302323 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000635
vccbram_static_current=0.001165 vccbram_total_current=0.001800 vccbram_voltage=1.000000 vccint_dynamic_current=0.110992
vccint_static_current=0.019014 vccint_total_current=0.130006 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.237182
vcco18_static_current=0.004000 vcco18_total_current=0.241182 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.009273
vcco33_static_current=0.004000 vcco33_total_current=0.013273 vcco33_voltage=3.300000 version=2021.1
xadc=0.002089

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_prohibited=0 bufgctrl_used=4
bufgctrl_util_percentage=12.50 bufhce_available=96 bufhce_fixed=0 bufhce_prohibited=0
bufhce_used=1 bufhce_util_percentage=1.04 bufio_available=24 bufio_fixed=0
bufio_prohibited=0 bufio_used=0 bufio_util_percentage=0.00 bufmrce_available=12
bufmrce_fixed=0 bufmrce_prohibited=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_prohibited=0 bufr_used=0
bufr_util_percentage=0.00 mmcme2_adv_available=6 mmcme2_adv_fixed=1 mmcme2_adv_prohibited=0
mmcme2_adv_used=1 mmcme2_adv_util_percentage=16.67 plle2_adv_available=6 plle2_adv_fixed=1
plle2_adv_prohibited=0 plle2_adv_used=2 plle2_adv_util_percentage=33.33
dsp
dsp48e1_only_used=4 dsps_available=240 dsps_fixed=0 dsps_prohibited=0
dsps_used=4 dsps_util_percentage=1.67
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=1 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=1
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_prohibited=0 block_ram_tile_used=32.5
block_ram_tile_util_percentage=24.07 ramb18_available=270 ramb18_fixed=0 ramb18_prohibited=0
ramb18_used=1 ramb18_util_percentage=0.37 ramb18e1_only_used=1 ramb36_fifo_available=135
ramb36_fifo_fixed=0 ramb36_fifo_prohibited=0 ramb36_fifo_used=32 ramb36_fifo_util_percentage=23.70
ramb36e1_only_used=32
primitives
bufg_functional_category=Clock bufg_used=4 bufh_functional_category=Clock bufh_used=1
carry4_functional_category=CarryLogic carry4_used=579 dsp48e1_functional_category=Block Arithmetic dsp48e1_used=4
fdce_functional_category=Flop & Latch fdce_used=103 fdpe_functional_category=Flop & Latch fdpe_used=51
fdre_functional_category=Flop & Latch fdre_used=5135 fdse_functional_category=Flop & Latch fdse_used=124
ibuf_functional_category=IO ibuf_intermdisable_functional_category=IO ibuf_intermdisable_used=16 ibuf_used=29
ibufds_intermdisable_int_functional_category=IO ibufds_intermdisable_int_used=4 idelayctrl_functional_category=IO idelayctrl_used=1
idelaye2_functional_category=IO idelaye2_used=16 in_fifo_functional_category=IO in_fifo_used=2
inv_functional_category=LUT inv_used=3 iserdese2_functional_category=IO iserdese2_used=16
lut1_functional_category=LUT lut1_used=592 lut2_functional_category=LUT lut2_used=1563
lut3_functional_category=LUT lut3_used=1089 lut4_functional_category=LUT lut4_used=1418
lut5_functional_category=LUT lut5_used=1552 lut6_functional_category=LUT lut6_used=3169
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=271
muxf8_functional_category=MuxFx muxf8_used=53 obuf_functional_category=IO obuf_used=80
obufds_functional_category=IO obufds_used=2 obuft_functional_category=IO obuft_used=23
obuftds_functional_category=IO obuftds_used=4 oddr_functional_category=IO oddr_used=5
oserdese2_functional_category=IO oserdese2_used=42 out_fifo_functional_category=IO out_fifo_used=4
phaser_in_phy_functional_category=IO phaser_in_phy_used=2 phaser_out_phy_functional_category=IO phaser_out_phy_used=4
phaser_ref_functional_category=IO phaser_ref_used=1 phy_control_functional_category=IO phy_control_used=1
plle2_adv_functional_category=Clock plle2_adv_used=2 ramb18e1_functional_category=Block Memory ramb18e1_used=1
ramb36e1_functional_category=Block Memory ramb36e1_used=32 ramd32_functional_category=Distributed Memory ramd32_used=570
rams32_functional_category=Distributed Memory rams32_used=186 srl16e_functional_category=Distributed Memory srl16e_used=42
srlc32e_functional_category=Distributed Memory srlc32e_used=12 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_prohibited=0 f7_muxes_used=271
f7_muxes_util_percentage=0.85 f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_prohibited=0
f8_muxes_used=53 f8_muxes_util_percentage=0.33 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=378
lut_as_logic_available=63400 lut_as_logic_fixed=0 lut_as_logic_prohibited=0 lut_as_logic_used=7630
lut_as_logic_util_percentage=12.03 lut_as_memory_available=19000 lut_as_memory_fixed=0 lut_as_memory_prohibited=0
lut_as_memory_used=427 lut_as_memory_util_percentage=2.25 lut_as_shift_register_fixed=0 lut_as_shift_register_used=49
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_prohibited=0 register_as_flip_flop_used=5413
register_as_flip_flop_util_percentage=4.27 register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_prohibited=0
register_as_latch_used=0 register_as_latch_util_percentage=0.00 slice_luts_available=63400 slice_luts_fixed=0
slice_luts_prohibited=0 slice_luts_used=8057 slice_luts_util_percentage=12.71 slice_registers_available=126800
slice_registers_fixed=0 slice_registers_prohibited=0 slice_registers_used=5413 slice_registers_util_percentage=4.27
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=378 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_prohibited=0 lut_as_logic_used=7630 lut_as_logic_util_percentage=12.03 lut_as_memory_available=19000
lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=427 lut_as_memory_util_percentage=2.25
lut_as_shift_register_fixed=0 lut_as_shift_register_used=49 lut_in_front_of_the_register_is_unused_available=49 lut_in_front_of_the_register_is_unused_fixed=49
lut_in_front_of_the_register_is_unused_prohibited=49 lut_in_front_of_the_register_is_unused_used=1168 lut_in_front_of_the_register_is_used_available=1168 lut_in_front_of_the_register_is_used_fixed=1168
lut_in_front_of_the_register_is_used_prohibited=1168 lut_in_front_of_the_register_is_used_used=924 register_driven_from_outside_the_slice_fixed=924 register_driven_from_outside_the_slice_used=2092
register_driven_from_within_the_slice_fixed=2092 register_driven_from_within_the_slice_used=3321 slice_available=15850 slice_fixed=0
slice_prohibited=0 slice_registers_available=126800 slice_registers_fixed=0 slice_registers_prohibited=0
slice_registers_used=5413 slice_registers_util_percentage=4.27 slice_used=2894 slice_util_percentage=18.26
slicel_fixed=0 slicel_used=2004 slicem_fixed=0 slicem_used=890
unique_control_sets_available=15850 unique_control_sets_fixed=15850 unique_control_sets_prohibited=0 unique_control_sets_used=243
unique_control_sets_util_percentage=1.53 using_o5_and_o6_available=1.53 using_o5_and_o6_fixed=1.53 using_o5_and_o6_prohibited=1.53
using_o5_and_o6_used=5 using_o5_output_only_available=5 using_o5_output_only_fixed=5 using_o5_output_only_prohibited=5
using_o5_output_only_used=16 using_o6_output_only_available=16 using_o6_output_only_fixed=16 using_o6_output_only_prohibited=16
using_o6_output_only_used=28
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_prohibited=0 bscane2_used=0
bscane2_util_percentage=0.00 capturee2_available=1 capturee2_fixed=0 capturee2_prohibited=0
capturee2_used=0 capturee2_util_percentage=0.00 dna_port_available=1 dna_port_fixed=0
dna_port_prohibited=0 dna_port_used=0 dna_port_util_percentage=0.00 efuse_usr_available=1
efuse_usr_fixed=0 efuse_usr_prohibited=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_prohibited=0 frame_ecce2_used=0
frame_ecce2_util_percentage=0.00 icape2_available=2 icape2_fixed=0 icape2_prohibited=0
icape2_used=0 icape2_util_percentage=0.00 pcie_2_1_available=1 pcie_2_1_fixed=0
pcie_2_1_prohibited=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00 startupe2_available=1
startupe2_fixed=0 startupe2_prohibited=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_prohibited=0 xadc_used=1
xadc_util_percentage=100.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -incremental=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified]
-max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1
-max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified]
-no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7a100tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=Nexys4DdrUserDemo -verilog_define=default::[not_specified]
usage
elapsed=00:16:36s hls_ip=0 memory_gain=2605.051MB memory_peak=3862.551MB