Name |
Value |
C_DCM1_RST_MODULE |
NONE |
C_DCM1_STARTUP_WAIT |
false |
C_DCM2_CLK0_BUF |
false |
C_DCM2_CLK180_BUF |
false |
C_DCM2_CLK270_BUF |
false |
C_DCM2_CLK2X180_BUF |
false |
C_DCM2_CLK2X_BUF |
false |
C_DCM2_CLK90_BUF |
false |
C_DCM2_CLKDV180_BUF |
false |
C_DCM2_CLKDV_BUF |
false |
C_DCM2_CLKDV_DIVIDE |
2.000000 |
C_DCM2_CLKFB_BUF |
false |
C_DCM2_CLKFB_MODULE |
NONE |
C_DCM2_CLKFB_PORT |
NONE |
C_DCM2_CLKFX180_BUF |
false |
C_DCM2_CLKFX_BUF |
false |
C_DCM2_CLKFX_DIVIDE |
1 |
C_DCM2_CLKFX_MULTIPLY |
4 |
C_DCM2_CLKIN_BUF |
false |
C_DCM2_CLKIN_DIVIDE_BY_2 |
false |
C_DCM2_CLKIN_MODULE |
NONE |
C_DCM2_CLKIN_PERIOD |
0.000000 |
C_DCM2_CLKIN_PORT |
NONE |
C_DCM2_CLKOUT_PHASE_SHIFT |
NONE |
C_DCM2_CLK_FEEDBACK |
1X |
C_DCM2_DESKEW_ADJUST |
SYSTEM_SYNCHRONOUS |
C_DCM2_DFS_FREQUENCY_MODE |
LOW |
C_DCM2_DLL_FREQUENCY_MODE |
LOW |
C_DCM2_DSS_MODE |
NONE |
C_DCM2_DUTY_CYCLE_CORRECTION |
true |
C_DCM2_EXT_RESET_HIGH |
1 |
C_DCM2_FAMILY |
virtex5 |
C_DCM2_PHASE_SHIFT |
0 |
C_DCM2_RST_MODULE |
NONE |
C_DCM2_STARTUP_WAIT |
false |
C_DCM3_CLK0_BUF |
false |
C_DCM3_CLK180_BUF |
false |
C_DCM3_CLK270_BUF |
false |
C_DCM3_CLK2X180_BUF |
false |
C_DCM3_CLK2X_BUF |
false |
C_DCM3_CLK90_BUF |
false |
C_DCM3_CLKDV180_BUF |
false |
C_DCM3_CLKDV_BUF |
false |
C_DCM3_CLKDV_DIVIDE |
2.000000 |
C_DCM3_CLKFB_BUF |
false |
C_DCM3_CLKFB_MODULE |
NONE |
C_DCM3_CLKFB_PORT |
NONE |
C_DCM3_CLKFX180_BUF |
false |
C_DCM3_CLKFX_BUF |
false |
C_DCM3_CLKFX_DIVIDE |
1 |
C_DCM3_CLKFX_MULTIPLY |
4 |
C_DCM3_CLKIN_BUF |
false |
C_DCM3_CLKIN_DIVIDE_BY_2 |
false |
C_DCM3_CLKIN_MODULE |
NONE |
C_DCM3_CLKIN_PERIOD |
0.000000 |
C_DCM3_CLKIN_PORT |
NONE |
C_DCM3_CLKOUT_PHASE_SHIFT |
NONE |
C_DCM3_CLK_FEEDBACK |
1X |
C_DCM3_DESKEW_ADJUST |
SYSTEM_SYNCHRONOUS |
C_DCM3_DFS_FREQUENCY_MODE |
LOW |
C_DCM3_DLL_FREQUENCY_MODE |
LOW |
C_DCM3_DSS_MODE |
NONE |
C_DCM3_DUTY_CYCLE_CORRECTION |
true |
C_DCM3_EXT_RESET_HIGH |
1 |
C_DCM3_FAMILY |
virtex5 |
C_DCM3_PHASE_SHIFT |
0 |
C_DCM3_RST_MODULE |
NONE |
C_DCM3_STARTUP_WAIT |
false |
C_EXT_RESET_HIGH |
1 |
C_PLL0_BANDWIDTH |
OPTIMIZED |
C_PLL0_CLKFBIN_MODULE |
NONE |
C_PLL0_CLKFBIN_PORT |
NONE |
C_PLL0_CLKFBOUT_BUF |
false |
C_PLL0_CLKFBOUT_DESKEW_ADJUST |
NONE |
C_PLL0_CLKFBOUT_MULT |
1 |
C_PLL0_CLKFBOUT_PHASE |
0.000000 |
C_PLL0_CLKIN1_BUF |
false |
C_PLL0_CLKIN1_MODULE |
NONE |
C_PLL0_CLKIN1_PERIOD |
0.000000 |
C_PLL0_CLKIN1_PORT |
NONE |
C_PLL0_CLKOUT0_BUF |
false |
C_PLL0_CLKOUT0_DESKEW_ADJUST |
NONE |
C_PLL0_CLKOUT0_DIVIDE |
1 |
C_PLL0_CLKOUT0_DUTY_CYCLE |
0.500000 |
C_PLL0_CLKOUT0_PHASE |
0.000000 |
C_PLL0_CLKOUT1_BUF |
false |
C_PLL0_CLKOUT1_DESKEW_ADJUST |
NONE |
C_PLL0_CLKOUT1_DIVIDE |
1 |
C_PLL0_CLKOUT1_DUTY_CYCLE |
0.500000 |
C_PLL0_CLKOUT1_PHASE |
0.000000 |
C_PLL0_CLKOUT2_BUF |
false |
C_PLL0_CLKOUT2_DESKEW_ADJUST |
NONE |
C_PLL0_CLKOUT2_DIVIDE |
1 |
C_PLL0_CLKOUT2_DUTY_CYCLE |
0.500000 |
C_PLL0_CLKOUT2_PHASE |
0.000000 |
C_PLL0_CLKOUT3_BUF |
false |
C_PLL0_CLKOUT3_DESKEW_ADJUST |
NONE |
C_PLL0_CLKOUT3_DIVIDE |
1 |
C_PLL0_CLKOUT3_DUTY_CYCLE |
0.500000 |
C_PLL0_CLKOUT3_PHASE |
0.000000 |
C_PLL0_CLKOUT4_BUF |
false |
C_PLL0_CLKOUT4_DESKEW_ADJUST |
NONE |
C_PLL0_CLKOUT4_DIVIDE |
1 |
C_PLL0_CLKOUT4_DUTY_CYCLE |
0.500000 |
C_PLL0_CLKOUT4_PHASE |
0.000000 |
C_PLL0_CLKOUT5_BUF |
false |
C_PLL0_CLKOUT5_DESKEW_ADJUST |
NONE |
C_PLL0_CLKOUT5_DIVIDE |
1 |
C_PLL0_CLKOUT5_DUTY_CYCLE |
0.500000 |
C_PLL0_CLKOUT5_PHASE |
0.000000 |
C_PLL0_COMPENSATION |
SYSTEM_SYNCHRONOUS |
C_PLL0_DIVCLK_DIVIDE |
1 |
C_PLL0_EXT_RESET_HIGH |
1 |
C_PLL0_FAMILY |
virtex5 |
C_PLL0_REF_JITTER |
0.100000 |
C_PLL0_RESET_ON_LOSS_OF_LOCK |
false |
C_PLL0_RST_DEASSERT_CLK |
CLKIN1 |
C_PLL0_RST_MODULE |
NONE |
C_PLL1_BANDWIDTH |
OPTIMIZED |
C_PLL1_CLKFBIN_MODULE |
NONE |
C_PLL1_CLKFBIN_PORT |
NONE |
C_PLL1_CLKFBOUT_BUF |
false |
C_PLL1_CLKFBOUT_DESKEW_ADJUST |
NONE |
C_PLL1_CLKFBOUT_MULT |
1 |
C_PLL1_CLKFBOUT_PHASE |
0.000000 |
C_PLL1_CLKIN1_BUF |
false |
C_PLL1_CLKIN1_MODULE |
NONE |
C_PLL1_CLKIN1_PERIOD |
0.000000 |
C_PLL1_CLKIN1_PORT |
NONE |
C_PLL1_CLKOUT0_BUF |
false |
C_PLL1_CLKOUT0_DESKEW_ADJUST |
NONE |
C_PLL1_CLKOUT0_DIVIDE |
1 |
C_PLL1_CLKOUT0_DUTY_CYCLE |
0.500000 |
C_PLL1_CLKOUT0_PHASE |
0.000000 |
C_PLL1_CLKOUT1_BUF |
false |
C_PLL1_CLKOUT1_DESKEW_ADJUST |
NONE |
C_PLL1_CLKOUT1_DIVIDE |
1 |
C_PLL1_CLKOUT1_DUTY_CYCLE |
0.500000 |
C_PLL1_CLKOUT1_PHASE |
0.000000 |
C_PLL1_CLKOUT2_BUF |
false |
C_PLL1_CLKOUT2_DESKEW_ADJUST |
NONE |
C_PLL1_CLKOUT2_DIVIDE |
1 |
C_PLL1_CLKOUT2_DUTY_CYCLE |
0.500000 |
C_PLL1_CLKOUT2_PHASE |
0.000000 |
C_PLL1_CLKOUT3_BUF |
false |
C_PLL1_CLKOUT3_DESKEW_ADJUST |
NONE |
C_PLL1_CLKOUT3_DIVIDE |
1 |
C_PLL1_CLKOUT3_DUTY_CYCLE |
0.500000 |
C_PLL1_CLKOUT3_PHASE |
0.000000 |
C_PLL1_CLKOUT4_BUF |
false |
C_PLL1_CLKOUT4_DESKEW_ADJUST |
NONE |
C_PLL1_CLKOUT4_DIVIDE |
1 |
C_PLL1_CLKOUT4_DUTY_CYCLE |
0.500000 |
C_PLL1_CLKOUT4_PHASE |
0.000000 |
C_PLL1_CLKOUT5_BUF |
false |
C_PLL1_CLKOUT5_DESKEW_ADJUST |
NONE |
C_PLL1_CLKOUT5_DIVIDE |
1 |
C_PLL1_CLKOUT5_DUTY_CYCLE |
0.500000 |
C_PLL1_CLKOUT5_PHASE |
0.000000 |
C_PLL1_COMPENSATION |
SYSTEM_SYNCHRONOUS |
C_PLL1_DIVCLK_DIVIDE |
1 |
C_PLL1_EXT_RESET_HIGH |
1 |
C_PLL1_FAMILY |
virtex5 |
C_PLL1_REF_JITTER |
0.100000 |
C_PLL1_RESET_ON_LOSS_OF_LOCK |
false |
C_PLL1_RST_DEASSERT_CLK |
CLKIN1 |
C_PLL1_RST_MODULE |
NONE |
C_SPEEDGRADE |
-4 |