Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version3247384
date_generatedWed Jul 27 16:00:02 2022 os_platformWIN64
product_versionVivado v2021.1 (64-bit) project_id5585c9f456c24eee95835be51ce86eac
project_iteration1 random_id98411614e97456ac81b93e31d34e0e7c
registration_id98411614e97456ac81b93e31d34e0e7c route_designTRUE
target_devicexc7a50ti target_familyartix7
target_packagecsg324 target_speed-1L
tool_flowVivado

user_environment
cpu_nameIntel(R) Xeon(R) Gold 6136 CPU @ 3.00GHz cpu_speed2993 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram343.000 GB total_processors2

vivado_usage
gui_handlers
basedialog_ok=1 basedialog_yes=1 commandsinput_type_tcl_command_here=1 flownavigatortreepanel_flow_navigator_tree=1
java_command_handlers
runbitgen=1
other_data
guimode=1
project_data
constraintsetcount=2 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=4 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=2 carry4=5 fdre=80 fdse=1
gnd=4 ibuf=3 lut1=4 lut2=4
lut3=11 lut4=14 lut5=4 lut6=19
muxf7=4 obuf=16 obuft=1 vcc=4
pre_unisim_transformation
bufg=2 carry4=5 fdre=80 fdse=1
gnd=4 ibuf=3 lut1=4 lut2=4
lut3=11 lut4=14 lut5=4 lut6=19
muxf7=4 obuf=16 obuft=1 vcc=4

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clocks=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=default::[not_specified] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=default::[not_specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_congestion_level=default::5 -min_level=default::[not_specified] -name=default::[not_specified]
-no_header=default::[not_specified] -of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=[specified]
-quiet=default::[not_specified] -return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified]
-routes=default::[not_specified] -setup=default::[not_specified] -show_all_congestion_windows=default::false -suggestion=default::[not_specified]
-timing=default::[not_specified] -verbose=default::[not_specified]
usage
runtime=0.049 secs
usage_count
qor_summary=4

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -merge_exceptions =default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified]
-return_string=default::[not_specified] -slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-17=56 timing-18=15 xdcc-4=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.000781 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Medium
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.061856
die=xc7a50ticsg324-1L dsp_output_toggle=12.500000 dynamic=0.015542 effective_thetaja=4.78
enable_probability=0.990000 family=artix7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.014150 input_toggle=12.500000 junction_temp=25.4 (C)
logic=0.000247 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.077399
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=csg324
pct_clock_constrained=1.000000 pct_inputs_defined=33 platform=nt64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.000364 simulation_file=None speedgrade=-1L
static_prob=False temp_grade=industrial thetajb=6.8 (C/W) thetasa=4.6 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.78 user_junc_temp=25.4 (C)
user_thetajb=6.8 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.018000
vccadc_total_current=0.018000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000516 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.011354
vccaux_total_current=0.011870 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000100
vccbram_total_current=0.000100 vccbram_voltage=0.950000 vccint_dynamic_current=0.001538 vccint_static_current=0.005920
vccint_total_current=0.007458 vccint_voltage=0.950000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.003986 vcco33_static_current=0.001000
vcco33_total_current=0.004986 vcco33_voltage=3.300000 version=2021.1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_prohibited=0 bufgctrl_used=2
bufgctrl_util_percentage=6.25 bufhce_available=72 bufhce_fixed=0 bufhce_prohibited=0
bufhce_used=0 bufhce_util_percentage=0.00 bufio_available=20 bufio_fixed=0
bufio_prohibited=0 bufio_used=0 bufio_util_percentage=0.00 bufmrce_available=10
bufmrce_fixed=0 bufmrce_prohibited=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_prohibited=0 bufr_used=0
bufr_util_percentage=0.00 mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_prohibited=0
mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00 plle2_adv_available=5 plle2_adv_fixed=0
plle2_adv_prohibited=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=120 dsps_fixed=0 dsps_prohibited=0 dsps_used=0
dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=75 block_ram_tile_fixed=0 block_ram_tile_prohibited=0 block_ram_tile_used=0
block_ram_tile_util_percentage=0.00 ramb18_available=150 ramb18_fixed=0 ramb18_prohibited=0
ramb18_used=0 ramb18_util_percentage=0.00 ramb36_fifo_available=75 ramb36_fifo_fixed=0
ramb36_fifo_prohibited=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=5
fdre_functional_category=Flop & Latch fdre_used=80 fdse_functional_category=Flop & Latch fdse_used=1
ibuf_functional_category=IO ibuf_used=3 lut1_functional_category=LUT lut1_used=4
lut2_functional_category=LUT lut2_used=4 lut3_functional_category=LUT lut3_used=11
lut4_functional_category=LUT lut4_used=14 lut5_functional_category=LUT lut5_used=4
lut6_functional_category=LUT lut6_used=19 muxf7_functional_category=MuxFx muxf7_used=4
obuf_functional_category=IO obuf_used=16 obuft_functional_category=IO obuft_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_prohibited=0 f7_muxes_used=4
f7_muxes_util_percentage=0.02 f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_prohibited=0
f8_muxes_used=0 f8_muxes_util_percentage=0.00 lut_as_logic_available=32600 lut_as_logic_fixed=0
lut_as_logic_prohibited=0 lut_as_logic_used=40 lut_as_logic_util_percentage=0.12 lut_as_memory_available=9600
lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=65200 register_as_flip_flop_fixed=0 register_as_flip_flop_prohibited=0 register_as_flip_flop_used=81
register_as_flip_flop_util_percentage=0.12 register_as_latch_available=65200 register_as_latch_fixed=0 register_as_latch_prohibited=0
register_as_latch_used=0 register_as_latch_util_percentage=0.00 slice_luts_available=32600 slice_luts_fixed=0
slice_luts_prohibited=0 slice_luts_used=40 slice_luts_util_percentage=0.12 slice_registers_available=65200
slice_registers_fixed=0 slice_registers_prohibited=0 slice_registers_used=81 slice_registers_util_percentage=0.12
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=32600 lut_as_logic_fixed=0
lut_as_logic_prohibited=0 lut_as_logic_used=40 lut_as_logic_util_percentage=0.12 lut_as_memory_available=9600
lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_in_front_of_the_register_is_unused_available=0 lut_in_front_of_the_register_is_unused_fixed=0
lut_in_front_of_the_register_is_unused_prohibited=0 lut_in_front_of_the_register_is_unused_used=27 lut_in_front_of_the_register_is_used_available=27 lut_in_front_of_the_register_is_used_fixed=27
lut_in_front_of_the_register_is_used_prohibited=27 lut_in_front_of_the_register_is_used_used=4 register_driven_from_outside_the_slice_fixed=4 register_driven_from_outside_the_slice_used=31
register_driven_from_within_the_slice_fixed=31 register_driven_from_within_the_slice_used=50 slice_available=8150 slice_fixed=0
slice_prohibited=0 slice_registers_available=65200 slice_registers_fixed=0 slice_registers_prohibited=0
slice_registers_used=81 slice_registers_util_percentage=0.12 slice_used=25 slice_util_percentage=0.31
slicel_fixed=0 slicel_used=19 slicem_fixed=0 slicem_used=6
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_prohibited=0 unique_control_sets_used=10
unique_control_sets_util_percentage=0.12 using_o5_and_o6_available=0.12 using_o5_and_o6_fixed=0.12 using_o5_and_o6_prohibited=0.12
using_o5_and_o6_used=16 using_o5_output_only_available=16 using_o5_output_only_fixed=16 using_o5_output_only_prohibited=16
using_o5_output_only_used=0 using_o6_output_only_available=0 using_o6_output_only_fixed=0 using_o6_output_only_prohibited=0
using_o6_output_only_used=24
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_prohibited=0 bscane2_used=0
bscane2_util_percentage=0.00 capturee2_available=1 capturee2_fixed=0 capturee2_prohibited=0
capturee2_used=0 capturee2_util_percentage=0.00 dna_port_available=1 dna_port_fixed=0
dna_port_prohibited=0 dna_port_used=0 dna_port_util_percentage=0.00 efuse_usr_available=1
efuse_usr_fixed=0 efuse_usr_prohibited=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_prohibited=0 frame_ecce2_used=0
frame_ecce2_util_percentage=0.00 icape2_available=2 icape2_fixed=0 icape2_prohibited=0
icape2_used=0 icape2_util_percentage=0.00 pcie_2_1_available=1 pcie_2_1_fixed=0
pcie_2_1_prohibited=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00 startupe2_available=1
startupe2_fixed=0 startupe2_prohibited=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_prohibited=0 xadc_used=0
xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=default::default -fanout_limit=default::10000
-flatten_hierarchy=default::rebuilt -fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -incremental=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified]
-max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1
-max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified]
-no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7a50ticsg324-1L
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=top -verilog_define=default::[not_specified]
usage
elapsed=00:00:32s hls_ip=0 memory_gain=33.805MB memory_peak=1291.180MB