Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version3247384
date_generatedThu Aug 25 14:32:38 2022 os_platformWIN64
product_versionVivado v2021.1 (64-bit) project_idb6cf4abca3e04b348c9fed1558015fc9
project_iteration1 random_idf1b197fcfcf756d8a9b8a0f5860629f1
registration_idf1b197fcfcf756d8a9b8a0f5860629f1 route_designTRUE
target_devicexc7a200t target_familyartix7
target_packagesbg484 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Xeon(R) CPU E5-1650 v2 @ 3.50GHz cpu_speed3492 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_ok=1 basedialog_yes=1 flownavigatortreepanel_flow_navigator_tree=1 mainmenumgr_tools=2
paviews_project_summary=1 rdicommands_run_script=1
java_command_handlers
runbitgen=1 runscript=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=3 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=19 totalsynthesisruns=19

unisim_transformation
post_unisim_transformation
and2b1l=14 bscane2=1 bufg=10 bufh=1
carry4=448 dsp48e1=5 fdce=189 fdpe=138
fdre=11686 fdse=481 gnd=845 ibuf=11
ibuf_intermdisable=16 ibufds_intermdisable_int=4 iddr=2 idelayctrl=1
idelaye2=16 in_fifo=2 inv=3 iserdese2=16
lut1=614 lut2=1257 lut3=2491 lut4=2497
lut5=3041 lut6=3866 mmcme2_adv=1 muxf7=177
obuf=29 obufds=2 obuft=20 obuftds=4
oddr=6 or2l=2 oserdese2=43 out_fifo=4
phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1 phy_control=1
plle2_adv=2 ramb18e1=3 ramb36e1=18 ramd32=962
rams32=272 srl16e=424 srlc16e=16 srlc32e=204
vcc=608 xadc=1
pre_unisim_transformation
and2b1l=14 bscane2=1 bufg=10 bufh=1
carry4=448 dsp48e1=5 fdce=189 fdpe=138
fdre=11686 fdse=481 gnd=845 ibuf=9
iddr=2 idelayctrl=1 idelaye2=16 in_fifo=2
iobuf=2 iobuf_intermdisable=16 iobufds_diff_out_intermdisable=2 iserdese2=16
lut1=614 lut2=1257 lut3=2491 lut4=2497
lut5=2937 lut6=3762 lut6_2=104 mmcme2_adv=1
muxf7=177 obuf=29 obufds=1 obuft=2
oddr=6 or2l=2 oserdese2=43 out_fifo=4
phaser_in_phy=2 phaser_out_phy=4 phaser_ref=1 phy_control=1
plle2_adv=2 ram32m=136 ram32x1d=73 ramb18e1=3
ramb36e1=18 srl16e=424 srlc16e=16 srlc32e=204
vcc=608 xadc=1

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA iptotal=1 maxhierdepth=0
numblks=34 numhdlrefblks=0 numhierblks=15 numhlsblks=0
numnonxlnxblks=1 numpkgbdblks=0 numreposblks=19 numsysgenblks=0
synth_mode=OOC_per_IP x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=design_1
x_ipvendor=xilinx.com x_ipversion=1.00.a
MDM/1
x_ipversion=1.00.a c_addr_size=32 c_avoid_primitives=0 c_bscanid=76547328
c_data_size=32 c_dbg_mem_access=0 c_dbg_reg_access=0 c_debug_interface=0
c_ext_trig_reset_value=0xF1234 c_family=artix7 c_interconnect=2 c_jtag_chain=2
c_lmb_protocol=0 c_m_axi_addr_width=32 c_m_axi_data_width=32 c_m_axi_thread_id_width=1
c_m_axis_data_width=32 c_m_axis_id_width=7 c_mb_dbg_ports=1 c_s_axi_aclk_freq_hz=100000000
c_s_axi_addr_width=4 c_s_axi_data_width=32 c_trace_async_reset=0 c_trace_clk_freq_hz=200000000
c_trace_clk_out_phase=90 c_trace_data_width=32 c_trace_id=110 c_trace_output=0
c_trace_protocol=1 c_use_bscan=0 c_use_config_reset=0 c_use_cross_trigger=0
c_use_uart=0 core_container=NA iptotal=1 x_ipcorerevision=21
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=mdm x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.2
MicroBlaze/1
c_addr_tag_bits=16 c_allow_dcache_wr=1 c_allow_icache_wr=1 c_area_optimized=0
c_async_interrupt=1 c_async_wakeup=3 c_avoid_primitives=0 c_base_vectors=0x0000000000000000
c_branch_target_cache_size=0 c_cache_byte_size=8192 c_d_axi=1 c_d_lmb=1
c_d_lmb_protocol=0 c_daddr_size=32 c_data_size=32 c_dcache_addr_tag=16
c_dcache_always_used=1 c_dcache_baseaddr=0x0000000080000000 c_dcache_byte_size=8192 c_dcache_data_width=0
c_dcache_force_tag_lutram=0 c_dcache_highaddr=0x000000009fffffff c_dcache_line_len=8 c_dcache_use_writeback=0
c_dcache_victims=0 c_debug_counter_width=32 c_debug_enabled=1 c_debug_event_counters=5
c_debug_external_trace=0 c_debug_interface=0 c_debug_latency_counters=1 c_debug_profile_size=0
c_debug_trace_async_reset=0 c_debug_trace_size=8192 c_div_zero_exception=0 c_dynamic_bus_sizing=0
c_ecc_use_ce_exception=0 c_edge_is_positive=1 c_endianness=1 c_family=artix7
c_fault_tolerant=0 c_fpu_exception=0 c_freq=100000000 c_fsl_exception=0
c_fsl_links=0 c_i_axi=0 c_i_lmb=1 c_i_lmb_protocol=0
c_iaddr_size=32 c_icache_always_used=1 c_icache_baseaddr=0x0000000080000000 c_icache_data_width=0
c_icache_force_tag_lutram=0 c_icache_highaddr=0x000000009fffffff c_icache_line_len=8 c_icache_streams=0
c_icache_victims=0 c_ill_opcode_exception=0 c_imprecise_exceptions=0 c_instance=design_1_microblaze_0_0
c_instr_size=32 c_interconnect=2 c_interrupt_is_edge=0 c_lmb_data_size=32
c_lockstep_master=0 c_lockstep_slave=0 c_m0_axis_data_width=32 c_m10_axis_data_width=32
c_m11_axis_data_width=32 c_m12_axis_data_width=32 c_m13_axis_data_width=32 c_m14_axis_data_width=32
c_m15_axis_data_width=32 c_m1_axis_data_width=32 c_m2_axis_data_width=32 c_m3_axis_data_width=32
c_m4_axis_data_width=32 c_m5_axis_data_width=32 c_m6_axis_data_width=32 c_m7_axis_data_width=32
c_m8_axis_data_width=32 c_m9_axis_data_width=32 c_m_axi_d_bus_exception=1 c_m_axi_dc_addr_width=32
c_m_axi_dc_aruser_width=5 c_m_axi_dc_awuser_width=5 c_m_axi_dc_buser_width=1 c_m_axi_dc_data_width=32
c_m_axi_dc_exclusive_access=0 c_m_axi_dc_ruser_width=1 c_m_axi_dc_thread_id_width=1 c_m_axi_dc_user_value=31
c_m_axi_dc_wuser_width=1 c_m_axi_dp_addr_width=32 c_m_axi_dp_data_width=32 c_m_axi_dp_exclusive_access=0
c_m_axi_dp_thread_id_width=1 c_m_axi_i_bus_exception=0 c_m_axi_ic_addr_width=32 c_m_axi_ic_aruser_width=5
c_m_axi_ic_awuser_width=5 c_m_axi_ic_buser_width=1 c_m_axi_ic_data_width=32 c_m_axi_ic_ruser_width=1
c_m_axi_ic_thread_id_width=1 c_m_axi_ic_user_value=31 c_m_axi_ic_wuser_width=1 c_m_axi_ip_addr_width=32
c_m_axi_ip_data_width=32 c_m_axi_ip_thread_id_width=1 c_mmu_dtlb_size=4 c_mmu_itlb_size=2
c_mmu_privileged_instr=0 c_mmu_tlb_access=3 c_mmu_zones=2 c_num_sync_ff_clk=2
c_num_sync_ff_clk_debug=2 c_num_sync_ff_clk_irq=1 c_num_sync_ff_dbg_clk=1 c_num_sync_ff_dbg_trace_clk=2
c_number_of_pc_brk=2 c_number_of_rd_addr_brk=0 c_number_of_wr_addr_brk=0 c_opcode_0x0_illegal=0
c_optimization=0 c_pc_width=32 c_piaddr_size=32 c_pvr=0
c_pvr_user1=0x00 c_pvr_user2=0x00000000 c_reset_msr=0x00000000 c_s0_axis_data_width=32
c_s10_axis_data_width=32 c_s11_axis_data_width=32 c_s12_axis_data_width=32 c_s13_axis_data_width=32
c_s14_axis_data_width=32 c_s15_axis_data_width=32 c_s1_axis_data_width=32 c_s2_axis_data_width=32
c_s3_axis_data_width=32 c_s4_axis_data_width=32 c_s5_axis_data_width=32 c_s6_axis_data_width=32
c_s7_axis_data_width=32 c_s8_axis_data_width=32 c_s9_axis_data_width=32 c_sco=0
c_unaligned_exceptions=0 c_use_barrel=0 c_use_branch_target_cache=0 c_use_config_reset=0
c_use_dcache=1 c_use_div=1 c_use_ext_brk=0 c_use_ext_nm_brk=0
c_use_extended_fsl_instr=0 c_use_fpu=1 c_use_hw_mul=1 c_use_icache=1
c_use_interrupt=2 c_use_mmu=0 c_use_msr_instr=1 c_use_non_secure=0
c_use_pcmp_instr=1 c_use_reorder_instr=1 c_use_stack_protection=0 core_container=NA
g_template_list=6 iptotal=1 x_ipcorerevision=6 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=microblaze x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=11.0
axi_crossbar_v2_1_25_axi_crossbar/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=2 c_axi_protocol=0 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=1 c_family=artix7
c_m_axi_addr_width=0x0000001d c_m_axi_base_addr=0x0000000080000000 c_m_axi_read_connectivity=0x00000007 c_m_axi_read_issuing=0x00000008
c_m_axi_secure=0x00000000 c_m_axi_write_connectivity=0x00000009 c_m_axi_write_issuing=0x00000008 c_num_addr_ranges=1
c_num_master_slots=1 c_num_slave_slots=4 c_r_register=0 c_s_axi_arb_priority=0x00000000000000000000000000000000
c_s_axi_base_id=0x00000003000000020000000100000000 c_s_axi_read_acceptance=0x00000002000000080000000200000002 c_s_axi_single_thread=0x00000000000000000000000000000000 c_s_axi_thread_id_width=0x00000000000000000000000000000000
c_s_axi_write_acceptance=0x00000008000000020000000200000008 core_container=NA iptotal=1 x_ipcorerevision=25
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_crossbar_v2_1_25_axi_crossbar/2
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=1 c_axi_protocol=2 c_axi_ruser_width=1
c_axi_supports_user_signals=0 c_axi_wuser_width=1 c_connectivity_mode=0 c_family=artix7
c_m_axi_addr_width=0x000000100000001000000010000000100000001000000010 c_m_axi_base_addr=0x000000004000000000000000408000000000000044a0000000000000406000000000000041e000000000000041200000 c_m_axi_read_connectivity=0x000000010000000100000001000000010000000100000001 c_m_axi_read_issuing=0x000000010000000100000001000000010000000100000001
c_m_axi_secure=0x000000000000000000000000000000000000000000000000 c_m_axi_write_connectivity=0x000000010000000100000001000000010000000100000001 c_m_axi_write_issuing=0x000000010000000100000001000000010000000100000001 c_num_addr_ranges=1
c_num_master_slots=6 c_num_slave_slots=1 c_r_register=1 c_s_axi_arb_priority=0x00000000
c_s_axi_base_id=0x00000000 c_s_axi_read_acceptance=0x00000001 c_s_axi_single_thread=0x00000001 c_s_axi_thread_id_width=0x00000000
c_s_axi_write_acceptance=0x00000001 core_container=NA iptotal=1 x_ipcorerevision=25
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_crossbar x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
axi_dma/1
c_dlytmr_resolution=125 c_enable_multi_channel=0 c_family=artix7 c_include_mm2s=1
c_include_mm2s_dre=0 c_include_mm2s_sf=1 c_include_s2mm=1 c_include_s2mm_dre=0
c_include_s2mm_sf=1 c_include_sg=0 c_increase_throughput=0 c_m_axi_mm2s_addr_width=32
c_m_axi_mm2s_data_width=32 c_m_axi_s2mm_addr_width=32 c_m_axi_s2mm_data_width=32 c_m_axi_sg_addr_width=32
c_m_axi_sg_data_width=32 c_m_axis_mm2s_cntrl_tdata_width=32 c_m_axis_mm2s_tdata_width=32 c_micro_dma=0
c_mm2s_burst_size=256 c_num_mm2s_channels=1 c_num_s2mm_channels=1 c_prmry_is_aclk_async=0
c_s2mm_burst_size=256 c_s_axi_lite_addr_width=10 c_s_axi_lite_data_width=32 c_s_axis_s2mm_sts_tdata_width=32
c_s_axis_s2mm_tdata_width=32 c_sg_include_stscntrl_strm=0 c_sg_length_width=23 c_sg_use_stsapp_length=0
core_container=NA iptotal=1 x_ipcorerevision=25 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_dma x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=7.1
axi_gpio/1
c_all_inputs=1 c_all_inputs_2=0 c_all_outputs=0 c_all_outputs_2=0
c_dout_default=0x00000000 c_dout_default_2=0x00000000 c_family=artix7 c_gpio2_width=32
c_gpio_width=5 c_interrupt_present=1 c_is_dual=0 c_s_axi_addr_width=9
c_s_axi_data_width=32 c_tri_default=0xFFFFFFFF c_tri_default_2=0xFFFFFFFF core_container=NA
iptotal=1 x_ipcorerevision=26 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axi_gpio x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.0
axi_iic/1
c_default_value=0x00 c_disable_setup_violation_check=0 c_family=artix7 c_gpo_width=1
c_iic_freq=100000 c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=9 c_s_axi_data_width=32
c_scl_inertial_delay=0 c_sda_inertial_delay=0 c_sda_level=1 c_smbus_pmbus_host=0
c_static_timing_reg_width=0 c_ten_bit_adr=0 c_timing_reg_width=32 core_container=NA
iptotal=1 x_ipcorerevision=0 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axi_iic x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=2.1
axi_intc/1
c_addr_width=32 c_async_intr=0xFFFFFFF0 c_cascade_master=0 c_disable_synchronizers=1
c_en_cascade_mode=0 c_enable_async=0 c_family=artix7 c_has_cie=1
c_has_fast=1 c_has_ilr=0 c_has_ipr=1 c_has_ivr=1
c_has_sie=1 c_instance=design_1_microblaze_0_axi_intc_0 c_irq_active=0x1 c_irq_is_level=1
c_ivar_reset_value=0x0000000000000010 c_kind_of_edge=0xFFFFFFFF c_kind_of_intr=0xfffffff0 c_kind_of_lvl=0xFFFFFFFF
c_mb_clk_not_connected=1 c_num_intr_inputs=4 c_num_sw_intr=0 c_num_sync_ff=2
c_s_axi_addr_width=9 c_s_axi_data_width=32 core_container=NA iptotal=1
x_ipcorerevision=15 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=axi_intc
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=4.1
axi_uartlite/1
c_baudrate=115200 c_data_bits=8 c_family=artix7 c_odd_parity=0
c_s_axi_aclk_freq_hz=100000000 c_s_axi_addr_width=4 c_s_axi_data_width=32 c_use_parity=0
core_container=NA iptotal=1 x_ipcorerevision=28 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_uartlite x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.0
blk_mem_gen_v8_4_4/1
c_addra_width=32 c_addrb_width=32 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=8 c_common_clk=0
c_count_18k_bram=0 c_count_36k_bram=2 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=1 c_est_power_summary=Estimated Power for IP _ 10.7492 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=1 c_has_enb=1
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=1
c_has_rstb=1 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=design_1_lmb_bram_0.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=2 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=2048 c_read_depth_b=2048 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=32 c_read_width_b=32 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=1
c_use_byte_wea=1 c_use_byte_web=1 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=4 c_web_width=4
c_write_depth_a=2048 c_write_depth_b=2048 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=32 c_write_width_b=32 c_xdevicefamily=artix7 core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
clk_wiz_v3_6/1
clkin1_period=10.000 clkin2_period=10.000 clock_mgr_type=MANUAL component_name=DCM
core_container=NA feedback_source=FDBK_AUTO feedback_type=SINGLE iptotal=1
manual_override=false num_out_clk=1 primtype_sel=MMCM_ADV use_clk_valid=false
use_dyn_phase_shift=false use_dyn_reconfig=false use_freeze=false use_inclk_stopped=false
use_inclk_switchover=false use_locked=true use_max_i_jitter=false use_min_o_jitter=false
use_phase_alignment=true use_power_down=false use_reset=true use_status=false
fifo_generator_v13_2_5/1
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=1 c_axi_len_width=8 c_axi_lock_width=1 c_axi_ruser_width=1
c_axi_type=1 c_axi_wuser_width=1 c_axis_tdata_width=8 c_axis_tdest_width=1
c_axis_tid_width=1 c_axis_tkeep_width=1 c_axis_tstrb_width=1 c_axis_tuser_width=4
c_axis_type=0 c_common_clock=0 c_count_type=0 c_data_count_width=12
c_default_value=BlankString c_din_width=24 c_din_width_axis=1 c_din_width_rach=32
c_din_width_rdch=64 c_din_width_wach=1 c_din_width_wdch=64 c_din_width_wrch=2
c_dout_rst_val=0 c_dout_width=24 c_en_safety_ckt=0 c_enable_rlocs=0
c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0 c_error_injection_type_rach=0
c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0 c_error_injection_type_wrch=0
c_family=artix7 c_full_flags_rst_val=1 c_has_almost_empty=0 c_has_almost_full=0
c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0 c_has_axi_id=0
c_has_axi_rd_channel=1 c_has_axi_ruser=0 c_has_axi_wr_channel=1 c_has_axi_wuser=0
c_has_axis_tdata=1 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=1
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_power_saving_mode=0 c_preload_latency=1
c_preload_regs=0 c_prim_fifo_type=4kx9 c_prim_fifo_type_axis=1kx18 c_prim_fifo_type_rach=512x36
c_prim_fifo_type_rdch=1kx36 c_prim_fifo_type_wach=512x36 c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36
c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022
c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022 c_prog_empty_thresh_negate_val=3
c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_full_thresh_assert_val=4093
c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_wach=1023
c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=4092 c_prog_full_type=0
c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0 c_rd_data_count_width=12
c_rd_depth=4096 c_rd_freq=1 c_rd_pntr_width=12 c_rdch_type=0
c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_select_xpm=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_use_pipeline_reg=0
c_valid_low=0 c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0
c_wr_data_count_width=12 c_wr_depth=4096 c_wr_depth_axis=1024 c_wr_depth_rach=16
c_wr_depth_rdch=1024 c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16
c_wr_freq=1 c_wr_pntr_width=12 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4
c_wr_pntr_width_rdch=10 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_response_latency=1 c_wrch_type=0 core_container=false iptotal=2
x_ipcorerevision=5 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=fifo_generator
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=13.2
fifo_generator_v13_2_5/2
c_add_ngc_constraint=0 c_application_type_axis=0 c_application_type_rach=0 c_application_type_rdch=0
c_application_type_wach=0 c_application_type_wdch=0 c_application_type_wrch=0 c_axi_addr_width=32
c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1 c_axi_data_width=64
c_axi_id_width=1 c_axi_len_width=8 c_axi_lock_width=1 c_axi_ruser_width=1
c_axi_type=1 c_axi_wuser_width=1 c_axis_tdata_width=8 c_axis_tdest_width=1
c_axis_tid_width=1 c_axis_tkeep_width=1 c_axis_tstrb_width=1 c_axis_tuser_width=4
c_axis_type=0 c_common_clock=0 c_count_type=0 c_data_count_width=4
c_default_value=BlankString c_din_width=4 c_din_width_axis=1 c_din_width_rach=32
c_din_width_rdch=64 c_din_width_wach=1 c_din_width_wdch=64 c_din_width_wrch=2
c_dout_rst_val=0 c_dout_width=4 c_en_safety_ckt=0 c_enable_rlocs=0
c_enable_rst_sync=1 c_error_injection_type=0 c_error_injection_type_axis=0 c_error_injection_type_rach=0
c_error_injection_type_rdch=0 c_error_injection_type_wach=0 c_error_injection_type_wdch=0 c_error_injection_type_wrch=0
c_family=artix7 c_full_flags_rst_val=1 c_has_almost_empty=0 c_has_almost_full=0
c_has_axi_aruser=0 c_has_axi_awuser=0 c_has_axi_buser=0 c_has_axi_id=0
c_has_axi_rd_channel=1 c_has_axi_ruser=0 c_has_axi_wr_channel=1 c_has_axi_wuser=0
c_has_axis_tdata=1 c_has_axis_tdest=0 c_has_axis_tid=0 c_has_axis_tkeep=0
c_has_axis_tlast=0 c_has_axis_tready=1 c_has_axis_tstrb=0 c_has_axis_tuser=1
c_has_backup=0 c_has_data_count=0 c_has_data_counts_axis=0 c_has_data_counts_rach=0
c_has_data_counts_rdch=0 c_has_data_counts_wach=0 c_has_data_counts_wdch=0 c_has_data_counts_wrch=0
c_has_int_clk=0 c_has_master_ce=0 c_has_meminit_file=0 c_has_overflow=0
c_has_prog_flags_axis=0 c_has_prog_flags_rach=0 c_has_prog_flags_rdch=0 c_has_prog_flags_wach=0
c_has_prog_flags_wdch=0 c_has_prog_flags_wrch=0 c_has_rd_data_count=0 c_has_rd_rst=0
c_has_rst=1 c_has_slave_ce=0 c_has_srst=0 c_has_underflow=0
c_has_valid=0 c_has_wr_ack=0 c_has_wr_data_count=0 c_has_wr_rst=0
c_implementation_type=2 c_implementation_type_axis=1 c_implementation_type_rach=1 c_implementation_type_rdch=1
c_implementation_type_wach=1 c_implementation_type_wdch=1 c_implementation_type_wrch=1 c_init_wr_pntr_val=0
c_interface_type=0 c_memory_type=1 c_mif_file_name=BlankString c_msgon_val=1
c_optimization_mode=0 c_overflow_low=0 c_power_saving_mode=0 c_preload_latency=1
c_preload_regs=0 c_prim_fifo_type=512x36 c_prim_fifo_type_axis=1kx18 c_prim_fifo_type_rach=512x36
c_prim_fifo_type_rdch=1kx36 c_prim_fifo_type_wach=512x36 c_prim_fifo_type_wdch=1kx36 c_prim_fifo_type_wrch=512x36
c_prog_empty_thresh_assert_val=2 c_prog_empty_thresh_assert_val_axis=1022 c_prog_empty_thresh_assert_val_rach=1022 c_prog_empty_thresh_assert_val_rdch=1022
c_prog_empty_thresh_assert_val_wach=1022 c_prog_empty_thresh_assert_val_wdch=1022 c_prog_empty_thresh_assert_val_wrch=1022 c_prog_empty_thresh_negate_val=3
c_prog_empty_type=0 c_prog_empty_type_axis=0 c_prog_empty_type_rach=0 c_prog_empty_type_rdch=0
c_prog_empty_type_wach=0 c_prog_empty_type_wdch=0 c_prog_empty_type_wrch=0 c_prog_full_thresh_assert_val=13
c_prog_full_thresh_assert_val_axis=1023 c_prog_full_thresh_assert_val_rach=1023 c_prog_full_thresh_assert_val_rdch=1023 c_prog_full_thresh_assert_val_wach=1023
c_prog_full_thresh_assert_val_wdch=1023 c_prog_full_thresh_assert_val_wrch=1023 c_prog_full_thresh_negate_val=12 c_prog_full_type=0
c_prog_full_type_axis=0 c_prog_full_type_rach=0 c_prog_full_type_rdch=0 c_prog_full_type_wach=0
c_prog_full_type_wdch=0 c_prog_full_type_wrch=0 c_rach_type=0 c_rd_data_count_width=4
c_rd_depth=16 c_rd_freq=1 c_rd_pntr_width=4 c_rdch_type=0
c_reg_slice_mode_axis=0 c_reg_slice_mode_rach=0 c_reg_slice_mode_rdch=0 c_reg_slice_mode_wach=0
c_reg_slice_mode_wdch=0 c_reg_slice_mode_wrch=0 c_select_xpm=0 c_synchronizer_stage=2
c_underflow_low=0 c_use_common_overflow=0 c_use_common_underflow=0 c_use_default_settings=0
c_use_dout_rst=1 c_use_ecc=0 c_use_ecc_axis=0 c_use_ecc_rach=0
c_use_ecc_rdch=0 c_use_ecc_wach=0 c_use_ecc_wdch=0 c_use_ecc_wrch=0
c_use_embedded_reg=0 c_use_fifo16_flags=0 c_use_fwft_data_count=0 c_use_pipeline_reg=0
c_valid_low=0 c_wach_type=0 c_wdch_type=0 c_wr_ack_low=0
c_wr_data_count_width=4 c_wr_depth=16 c_wr_depth_axis=1024 c_wr_depth_rach=16
c_wr_depth_rdch=1024 c_wr_depth_wach=16 c_wr_depth_wdch=1024 c_wr_depth_wrch=16
c_wr_freq=1 c_wr_pntr_width=4 c_wr_pntr_width_axis=10 c_wr_pntr_width_rach=4
c_wr_pntr_width_rdch=10 c_wr_pntr_width_wach=4 c_wr_pntr_width_wdch=10 c_wr_pntr_width_wrch=4
c_wr_response_latency=1 c_wrch_type=0 core_container=false iptotal=1
x_ipcorerevision=5 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=fifo_generator
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=13.2
lmb_bram_if_cntlr/1
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000001FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_protocol=0 c_mask=0x00000000c0000000
c_mask1=0x0000000000800000 c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2
core_container=NA iptotal=1 x_ipcorerevision=19 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=4.0
lmb_bram_if_cntlr/2
c_baseaddr=0x0000000000000000 c_bram_awidth=32 c_ce_counter_width=0 c_ce_failing_registers=0
c_ecc=0 c_ecc_onoff_register=0 c_ecc_onoff_reset_value=1 c_ecc_status_registers=0
c_family=artix7 c_fault_inject=0 c_highaddr=0x0000000000001FFF c_interconnect=0
c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_protocol=0 c_mask=0x0000000080000000
c_mask1=0x0000000000800000 c_mask2=0x0000000000800000 c_mask3=0x0000000000800000 c_num_lmb=1
c_s_axi_ctrl_addr_width=32 c_s_axi_ctrl_data_width=32 c_ue_failing_registers=0 c_write_access=2
core_container=NA iptotal=1 x_ipcorerevision=19 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=lmb_bram_if_cntlr x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=4.0
lmb_v10/1
c_ext_reset_high=1 c_lmb_awidth=32 c_lmb_dwidth=32 c_lmb_num_slaves=1
c_lmb_protocol=0 core_container=NA iptotal=2 x_ipcorerevision=11
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=lmb_v10 x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=3.0
mig_7series_v4_2/1
axi_enable=1 burst_mode=8 burst_type=SEQ ca_mirror=OFF
clk_period=2500 clkin_period=10000 core_container=NA data_mask=1
debug_port=OFF dq_width=16 ecc=OFF interface_type=DDR3
internal_vref=1 iptotal=1 language=Verilog level=CONTROLLER
memory_address_map=BANK_ROW_COLUMN memory_part=mt41k256m16xx-125 memory_type=COMP no_of_controllers=1
ordering=NORM output_drv=HIGH phy_ratio=4 refclk_freq=200
refclk_type=NO_BUFFER rtt_nom=40 synthesis_tool=Vivado sysclk_type=SINGLE_ENDED
use_cs_port=0 use_odt_port=1 vccaux_io=1.8V
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=artix7 c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=13
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
proc_sys_reset/2
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=1 c_ext_rst_width=4
c_family=artix7 c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=13
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2021.1
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
xlconcat_v2_1_4_xlconcat/1
core_container=NA dout_width=4 in0_width=1 in100_width=1
in101_width=1 in102_width=1 in103_width=1 in104_width=1
in105_width=1 in106_width=1 in107_width=1 in108_width=1
in109_width=1 in10_width=1 in110_width=1 in111_width=1
in112_width=1 in113_width=1 in114_width=1 in115_width=1
in116_width=1 in117_width=1 in118_width=1 in119_width=1
in11_width=1 in120_width=1 in121_width=1 in122_width=1
in123_width=1 in124_width=1 in125_width=1 in126_width=1
in127_width=1 in12_width=1 in13_width=1 in14_width=1
in15_width=1 in16_width=1 in17_width=1 in18_width=1
in19_width=1 in1_width=1 in20_width=1 in21_width=1
in22_width=1 in23_width=1 in24_width=1 in25_width=1
in26_width=1 in27_width=1 in28_width=1 in29_width=1
in2_width=1 in30_width=1 in31_width=1 in32_width=1
in33_width=1 in34_width=1 in35_width=1 in36_width=1
in37_width=1 in38_width=1 in39_width=1 in3_width=1
in40_width=1 in41_width=1 in42_width=1 in43_width=1
in44_width=1 in45_width=1 in46_width=1 in47_width=1
in48_width=1 in49_width=1 in4_width=1 in50_width=1
in51_width=1 in52_width=1 in53_width=1 in54_width=1
in55_width=1 in56_width=1 in57_width=1 in58_width=1
in59_width=1 in5_width=1 in60_width=1 in61_width=1
in62_width=1 in63_width=1 in64_width=1 in65_width=1
in66_width=1 in67_width=1 in68_width=1 in69_width=1
in6_width=1 in70_width=1 in71_width=1 in72_width=1
in73_width=1 in74_width=1 in75_width=1 in76_width=1
in77_width=1 in78_width=1 in79_width=1 in7_width=1
in80_width=1 in81_width=1 in82_width=1 in83_width=1
in84_width=1 in85_width=1 in86_width=1 in87_width=1
in88_width=1 in89_width=1 in8_width=1 in90_width=1
in91_width=1 in92_width=1 in93_width=1 in94_width=1
in95_width=1 in96_width=1 in97_width=1 in98_width=1
in99_width=1 in9_width=1 iptotal=1 num_ports=4
x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=xlconcat
x_ipproduct=Vivado 2021.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=2.1
xpm_cdc_async_rst/1
core_container=NA def_val=1'b0 dest_sync_ff=2 init_sync_ff=0
inv_def_val=1'b1 iptotal=6 rst_active_high=1 version=0
xpm_cdc_gray/1
core_container=NA dest_sync_ff=2 init_sync_ff=0 iptotal=6
reg_output=1 sim_assert_chk=0 sim_lossless_gray_chk=0 version=0
width=4
xpm_cdc_single/1
core_container=NA dest_sync_ff=4 init_sync_ff=0 iptotal=6
sim_assert_chk=0 src_input_reg=0 version=0
xpm_fifo_base/1
both_stages_valid=3 cascade_height=0 cdc_dest_sync_ff=2 common_clock=1
core_container=NA dout_reset_value=0 ecc_mode=0 en_adv_feature=16'b0001111100011111
en_ae=1'b1 en_af=1'b1 en_dvld=1'b1 en_of=1'b1
en_pe=1'b1 en_pf=1'b1 en_rdc=1'b1 en_uf=1'b1
en_wack=1'b1 en_wdc=1'b1 enable_ecc=0 fg_eq_asym_dout=1'b0
fifo_mem_type=0 fifo_memory_type=0 fifo_read_depth=16 fifo_read_latency=0
fifo_size=208 fifo_write_depth=16 full_reset_value=1 full_rst_val=1'b1
invalid=0 iptotal=3 pe_thresh_adj=8 pe_thresh_max=11
pe_thresh_min=5 pf_thresh_adj=8 pf_thresh_max=11 pf_thresh_min=5
prog_empty_thresh=10 prog_full_thresh=10 rd_data_count_width=4 rd_dc_width_ext=5
rd_latency=2 rd_mode=1 rd_pntr_width=4 read_data_width=13
read_mode=1 read_mode_ll=1 related_clocks=0 remove_wr_rd_prot_logic=0
sim_assert_chk=0 stage1_valid=2 stage2_valid=1 use_adv_features=1F1F
version=0 wakeup_time=0 width_ratio=1 wr_data_count_width=5
wr_dc_width_ext=5 wr_depth_log=4 wr_pntr_width=4 wr_rd_ratio=0
wr_width_log=4 write_data_width=13
xpm_fifo_sync/1
cascade_height=0 core_container=NA dout_reset_value=0 ecc_mode=no_ecc
en_adv_feature_sync=16'b0001111100011111 fifo_memory_type=auto fifo_read_latency=0 fifo_write_depth=16
full_reset_value=1 iptotal=3 p_common_clock=1 p_ecc_mode=0
p_fifo_memory_type=0 p_read_mode=1 p_wakeup_time=2 prog_empty_thresh=10
prog_full_thresh=10 rd_data_count_width=4 read_data_width=13 read_mode=fwft
sim_assert_chk=0 use_adv_features=1F1F wakeup_time=0 wr_data_count_width=5
write_data_width=13
xpm_memory_base/1
write_data_width=13 addr_width_a=4 addr_width_b=4 auto_sleep_time=0
byte_write_width_a=13 byte_write_width_b=13 cascade_height=0 clocking_mode=0
core_container=NA ecc_mode=0 iptotal=3 max_num_char=0
memory_optimization=true memory_primitive=0 memory_size=208 memory_type=1
message_control=0 num_char_loc=0 p_ecc_mode=no_ecc p_enable_byte_write_a=0
p_enable_byte_write_b=0 p_max_depth_data=16 p_memory_opt=yes p_memory_primitive=auto
p_min_width_data=13 p_min_width_data_a=13 p_min_width_data_b=13 p_min_width_data_ecc=13
p_min_width_data_ldw=4 p_min_width_data_shft=13 p_num_cols_write_a=1 p_num_cols_write_b=1
p_num_rows_read_a=1 p_num_rows_read_b=1 p_num_rows_write_a=1 p_num_rows_write_b=1
p_sdp_write_mode=yes p_width_addr_lsb_read_a=0 p_width_addr_lsb_read_b=0 p_width_addr_lsb_write_a=0
p_width_addr_lsb_write_b=0 p_width_addr_read_a=4 p_width_addr_read_b=4 p_width_addr_write_a=4
p_width_addr_write_b=4 p_width_col_write_a=13 p_width_col_write_b=13 read_data_width_a=13
read_data_width_b=13 read_latency_a=2 read_latency_b=2 read_reset_value_a=0
read_reset_value_b=0 rst_mode_a=SYNC rst_mode_b=SYNC rsta_loop_iter=16
rstb_loop_iter=16 sim_assert_chk=0 use_embedded_constraint=0 use_mem_init=0
use_mem_init_mmi=0 version=0 wakeup_time=0 write_data_width_a=13
write_data_width_b=13 write_mode_a=2 write_mode_b=2 write_protect=1

report_design_analysis
command_line_options
-append=default::[not_specified] -bounding_boxes=default::[not_specified] -cells=default::[not_specified] -complexity=default::[not_specified]
-congestion=default::[not_specified] -end_point_clocks=default::[not_specified] -extend=default::[not_specified] -extract_metrics=default::[not_specified]
-file=default::[not_specified] -full_logical_pin=default::[not_specified] -hierarchical_depth=default::[not_specified] -hold=default::[not_specified]
-logic_level_dist_paths=default::[not_specified] -logic_level_distribution=default::[not_specified] -logic_levels=default::[not_specified] -max_level=default::[not_specified]
-max_paths=default::[not_specified] -min_congestion_level=default::5 -min_level=default::[not_specified] -name=default::[not_specified]
-no_header=default::[not_specified] -of_timing_paths=default::[not_specified] -pploc_distance=default::[not_specified] -qor_summary=[specified]
-quiet=default::[not_specified] -return_string=default::[not_specified] -return_timing_paths=default::[not_specified] -routed_vs_estimated=default::[not_specified]
-routes=default::[not_specified] -setup=default::[not_specified] -show_all_congestion_windows=default::false -suggestion=default::[not_specified]
-timing=default::[not_specified] -verbose=default::[not_specified]
usage
runtime=3.16 secs
usage_count
qor_summary=4

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -max_msgs_per_check=default::[not_specified]
-messages=default::[not_specified] -name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
bufc-1=2 cfgbvs-1=1 check-3=1 dpip-1=8
dpop-1=2 dpop-2=1 reqp-1709=1 reqp-1839=20
reqp-1840=16 rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -merge_exceptions =default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified]
-return_string=default::[not_specified] -slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
lutar-1=5 pdrc-190=12 reqp-1959=16 timing-18=11
timing-9=1 xdcb-5=3 xdcc-2=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.025609 clocks=0.064609
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=Low confidence_level_overall=Low customer=TBD customer_class=TBD
devstatic=0.151413 die=xc7a200tsbg484-1 dsp=0.003433 dsp_output_toggle=12.500000
dynamic=0.871898 effective_thetaja=3.31 enable_probability=0.990000 family=artix7
ff_toggle=12.500000 flow_state=routed heatsink=medium (Medium Profile) i/o=0.298490
input_toggle=12.500000 junction_temp=28.4 (C) logic=0.019347 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mmcm=0.095682
netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=1.023311 output_enable=1.000000
output_load=5.000000 output_toggle=12.500000 package=sbg484 pct_clock_constrained=23.000000
pct_inputs_defined=3 phaser=0.134441 platform=nt64 pll=0.200634
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.025773 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=5.0 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=3.31
user_junc_temp=28.4 (C) user_thetajb=5.0 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.001600
vccadc_static_current=0.020000 vccadc_total_current=0.021600 vccadc_voltage=1.800000 vccaux_dynamic_current=0.270385
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.030874 vccaux_total_current=0.301259 vccaux_voltage=1.800000 vccbram_dynamic_current=0.001935
vccbram_static_current=0.001306 vccbram_total_current=0.003241 vccbram_voltage=1.000000 vccint_dynamic_current=0.190079
vccint_static_current=0.034533 vccint_total_current=0.224612 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.125886
vcco15_static_current=0.005000 vcco15_total_current=0.130886 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000449
vcco33_static_current=0.005000 vcco33_total_current=0.005449 vcco33_voltage=3.300000 version=2021.1
xadc=0.003880

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_prohibited=0 bufgctrl_used=5
bufgctrl_util_percentage=15.63 bufhce_available=120 bufhce_fixed=0 bufhce_prohibited=0
bufhce_used=1 bufhce_util_percentage=0.83 bufio_available=40 bufio_fixed=0
bufio_prohibited=0 bufio_used=0 bufio_util_percentage=0.00 bufmrce_available=20
bufmrce_fixed=0 bufmrce_prohibited=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=40 bufr_fixed=0 bufr_prohibited=0 bufr_used=0
bufr_util_percentage=0.00 mmcme2_adv_available=10 mmcme2_adv_fixed=1 mmcme2_adv_prohibited=0
mmcme2_adv_used=1 mmcme2_adv_util_percentage=10.00 plle2_adv_available=10 plle2_adv_fixed=1
plle2_adv_prohibited=0 plle2_adv_used=2 plle2_adv_util_percentage=20.00
dsp
dsp48e1_only_used=5 dsps_available=740 dsps_fixed=0 dsps_prohibited=0
dsps_used=5 dsps_util_percentage=0.68
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=1 lvcmos15=1
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=1 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=365 block_ram_tile_fixed=0 block_ram_tile_prohibited=0 block_ram_tile_used=19.5
block_ram_tile_util_percentage=5.34 ramb18_available=730 ramb18_fixed=0 ramb18_prohibited=0
ramb18_used=3 ramb18_util_percentage=0.41 ramb18e1_only_used=3 ramb36_fifo_available=365
ramb36_fifo_fixed=0 ramb36_fifo_prohibited=0 ramb36_fifo_used=18 ramb36_fifo_util_percentage=4.93
ramb36e1_only_used=18
primitives
and2b1l_functional_category=Others and2b1l_used=14 bscane2_functional_category=Others bscane2_used=1
bufg_functional_category=Clock bufg_used=5 bufh_functional_category=Clock bufh_used=1
carry4_functional_category=CarryLogic carry4_used=447 dsp48e1_functional_category=Block Arithmetic dsp48e1_used=5
fdce_functional_category=Flop & Latch fdce_used=189 fdpe_functional_category=Flop & Latch fdpe_used=109
fdre_functional_category=Flop & Latch fdre_used=11490 fdse_functional_category=Flop & Latch fdse_used=478
ibuf_functional_category=IO ibuf_intermdisable_functional_category=IO ibuf_intermdisable_used=16 ibuf_used=11
ibufds_intermdisable_int_functional_category=IO ibufds_intermdisable_int_used=4 idelayctrl_functional_category=IO idelayctrl_used=1
idelaye2_functional_category=IO idelaye2_used=16 in_fifo_functional_category=IO in_fifo_used=2
inv_functional_category=LUT inv_used=3 iserdese2_functional_category=IO iserdese2_used=16
lut1_functional_category=LUT lut1_used=496 lut2_functional_category=LUT lut2_used=1241
lut3_functional_category=LUT lut3_used=2441 lut4_functional_category=LUT lut4_used=2474
lut5_functional_category=LUT lut5_used=3027 lut6_functional_category=LUT lut6_used=3697
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=177
obuf_functional_category=IO obuf_used=29 obufds_functional_category=IO obufds_used=2
obuft_functional_category=IO obuft_used=20 obuftds_functional_category=IO obuftds_used=4
oddr_functional_category=IO oddr_used=6 or2l_functional_category=Others or2l_used=2
oserdese2_functional_category=IO oserdese2_used=43 out_fifo_functional_category=IO out_fifo_used=4
phaser_in_phy_functional_category=IO phaser_in_phy_used=2 phaser_out_phy_functional_category=IO phaser_out_phy_used=4
phaser_ref_functional_category=IO phaser_ref_used=1 phy_control_functional_category=IO phy_control_used=1
plle2_adv_functional_category=Clock plle2_adv_used=2 ramb18e1_functional_category=Block Memory ramb18e1_used=3
ramb36e1_functional_category=Block Memory ramb36e1_used=18 ramd32_functional_category=Distributed Memory ramd32_used=962
rams32_functional_category=Distributed Memory rams32_used=272 srl16e_functional_category=Distributed Memory srl16e_used=429
srlc16e_functional_category=Distributed Memory srlc16e_used=14 srlc32e_functional_category=Distributed Memory srlc32e_used=191
xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=66900 f7_muxes_fixed=0 f7_muxes_prohibited=400 f7_muxes_used=177
f7_muxes_util_percentage=0.26 f8_muxes_available=33450 f8_muxes_fixed=0 f8_muxes_prohibited=200
f8_muxes_used=0 f8_muxes_util_percentage=0.00 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=618
lut_as_logic_available=133800 lut_as_logic_fixed=0 lut_as_logic_prohibited=800 lut_as_logic_used=11271
lut_as_logic_util_percentage=8.42 lut_as_memory_available=46200 lut_as_memory_fixed=0 lut_as_memory_prohibited=0
lut_as_memory_used=1089 lut_as_memory_util_percentage=2.36 lut_as_shift_register_fixed=0 lut_as_shift_register_used=471
register_as_and_or_available=269200 register_as_and_or_fixed=0 register_as_and_or_prohibited=0 register_as_and_or_used=16
register_as_and_or_util_percentage=<0.01 register_as_flip_flop_available=269200 register_as_flip_flop_fixed=2 register_as_flip_flop_prohibited=0
register_as_flip_flop_used=12266 register_as_flip_flop_util_percentage=4.56 register_as_latch_available=269200 register_as_latch_fixed=0
register_as_latch_prohibited=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00 slice_luts_available=133800
slice_luts_fixed=0 slice_luts_prohibited=800 slice_luts_used=12360 slice_luts_util_percentage=9.24
slice_registers_available=269200 slice_registers_fixed=2 slice_registers_prohibited=0 slice_registers_used=12282
slice_registers_util_percentage=4.56 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=618 lut_as_logic_available=133800
lut_as_logic_fixed=0 lut_as_logic_prohibited=800 lut_as_logic_used=11271 lut_as_logic_util_percentage=8.42
lut_as_memory_available=46200 lut_as_memory_fixed=0 lut_as_memory_prohibited=0 lut_as_memory_used=1089
lut_as_memory_util_percentage=2.36 lut_as_shift_register_fixed=0 lut_as_shift_register_used=471 lut_in_front_of_the_register_is_unused_available=471
lut_in_front_of_the_register_is_unused_fixed=471 lut_in_front_of_the_register_is_unused_prohibited=471 lut_in_front_of_the_register_is_unused_used=3376 lut_in_front_of_the_register_is_used_available=3376
lut_in_front_of_the_register_is_used_fixed=3376 lut_in_front_of_the_register_is_used_prohibited=3376 lut_in_front_of_the_register_is_used_used=2202 register_driven_from_outside_the_slice_fixed=2202
register_driven_from_outside_the_slice_used=5578 register_driven_from_within_the_slice_fixed=5578 register_driven_from_within_the_slice_used=6704 slice_available=33450
slice_fixed=0 slice_prohibited=200 slice_registers_available=269200 slice_registers_fixed=0
slice_registers_prohibited=0 slice_registers_used=12282 slice_registers_util_percentage=4.56 slice_used=4755
slice_util_percentage=14.22 slicel_fixed=0 slicel_used=3097 slicem_fixed=0
slicem_used=1658 unique_control_sets_available=33450 unique_control_sets_fixed=33450 unique_control_sets_prohibited=200
unique_control_sets_used=589 unique_control_sets_util_percentage=1.76 using_o5_and_o6_available=1.76 using_o5_and_o6_fixed=1.76
using_o5_and_o6_prohibited=1.76 using_o5_and_o6_used=163 using_o5_output_only_available=163 using_o5_output_only_fixed=163
using_o5_output_only_prohibited=163 using_o5_output_only_used=28 using_o6_output_only_available=28 using_o6_output_only_fixed=28
using_o6_output_only_prohibited=28 using_o6_output_only_used=280
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_prohibited=0 bscane2_used=1
bscane2_util_percentage=25.00 capturee2_available=1 capturee2_fixed=0 capturee2_prohibited=0
capturee2_used=0 capturee2_util_percentage=0.00 dna_port_available=1 dna_port_fixed=0
dna_port_prohibited=0 dna_port_used=0 dna_port_util_percentage=0.00 efuse_usr_available=1
efuse_usr_fixed=0 efuse_usr_prohibited=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_prohibited=0 frame_ecce2_used=0
frame_ecce2_util_percentage=0.00 icape2_available=2 icape2_fixed=0 icape2_prohibited=0
icape2_used=0 icape2_util_percentage=0.00 pcie_2_1_available=1 pcie_2_1_fixed=0
pcie_2_1_prohibited=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00 startupe2_available=1
startupe2_fixed=0 startupe2_prohibited=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_prohibited=0 xadc_used=1
xadc_util_percentage=100.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=RuntimeOptimized -fanout_limit=default::10000
-flatten_hierarchy=none -fsm_extraction=off -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -incremental=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -lint=default::[not_specified]
-max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1 -max_uram=default::-1
-max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified] -no_lc=default::[not_specified]
-no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -os=default::[not_specified] -part=xc7a200tsbg484-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:00:40s hls_ip=0 memory_gain=130.805MB memory_peak=1399.637MB