Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedTue Aug 23 15:00:20 2022 os_platformWIN64
product_versionVivado v2020.1 (64-bit) project_idbd7a3594188842e3ba8f79fba2817bdc
project_iteration1 random_id07d523fb0db453fc9d80a3d1ea7ae10f
registration_id07d523fb0db453fc9d80a3d1ea7ae10f route_designTRUE
target_devicexc7a200t target_familyartix7
target_packagesbg484 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Xeon(R) CPU E5-1650 v2 @ 3.50GHz cpu_speed3492 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram34.000 GB total_processors1

vivado_usage
gui_handlers
basedialog_ok=1 basedialog_yes=1 flownavigatortreepanel_flow_navigator_tree=1 mainmenumgr_tools=2
rdicommands_run_script=1
java_command_handlers
runbitgen=1 runscript=1
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=9 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=5 totalsynthesisruns=5

unisim_transformation
post_unisim_transformation
bufg=1 carry4=12 dsp48e1=1 fdre=287
fdse=8 gnd=18 ibuf=10 lut1=8
lut2=42 lut3=42 lut4=49 lut5=56
lut6=123 muxf7=6 obuf=6 ramb18e1=3
vcc=11 xadc=1
pre_unisim_transformation
bufg=1 carry4=12 dsp48e1=1 fdre=287
fdse=8 gnd=18 ibuf=10 lut1=8
lut2=42 lut3=42 lut4=49 lut5=56
lut6=123 muxf7=6 obuf=6 ramb18e1=3
vcc=11 xadc=1

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

ip_statistics
blk_mem_gen_v8_4_4/1
c_addra_width=10 c_addrb_width=10 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_count_18k_bram=1 c_count_36k_bram=0 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 1.1884 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=charLib.mem
c_init_file_name=[user-defined] c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=1 c_mem_type=3 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=1024 c_read_depth_b=1024 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=8 c_read_width_b=8 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=1 c_web_width=1
c_write_depth_a=1024 c_write_depth_b=1024 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=8 c_write_width_b=8 c_xdevicefamily=artix7 core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
blk_mem_gen_v8_4_4/2
c_addra_width=4 c_addrb_width=4 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=0
c_count_18k_bram=1 c_count_36k_bram=0 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 2.7096 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=init_sequence_rom.mem
c_init_file_name=[user-defined] c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=1 c_mem_type=3 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=16 c_read_depth_b=16 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=16 c_read_width_b=16 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=1 c_web_width=1
c_write_depth_a=16 c_write_depth_b=16 c_write_mode_a=WRITE_FIRST c_write_mode_b=WRITE_FIRST
c_write_width_a=16 c_write_width_b=16 c_xdevicefamily=artix7 core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
blk_mem_gen_v8_4_4/3
c_addra_width=9 c_addrb_width=9 c_algorithm=1 c_axi_id_width=4
c_axi_slave_type=0 c_axi_type=1 c_byte_size=9 c_common_clk=1
c_count_18k_bram=1 c_count_36k_bram=0 c_ctrl_ecc_algo=NONE c_default_data=0
c_disable_warn_bhv_coll=0 c_disable_warn_bhv_range=0 c_elaboration_dir=./ c_en_deepsleep_pin=0
c_en_ecc_pipe=0 c_en_rdaddra_chg=0 c_en_rdaddrb_chg=0 c_en_safety_ckt=0
c_en_shutdown_pin=0 c_en_sleep_pin=0 c_enable_32bit_address=0 c_est_power_summary=Estimated Power for IP _ 2.68455 mW
c_family=artix7 c_has_axi_id=0 c_has_ena=0 c_has_enb=0
c_has_injecterr=0 c_has_mem_output_regs_a=0 c_has_mem_output_regs_b=0 c_has_mux_output_regs_a=0
c_has_mux_output_regs_b=0 c_has_regcea=0 c_has_regceb=0 c_has_rsta=0
c_has_rstb=0 c_has_softecc_input_regs_a=0 c_has_softecc_output_regs_b=0 c_init_file=pixel_buffer.mem
c_init_file_name=no_coe_file_loaded c_inita_val=0 c_initb_val=0 c_interface_type=0
c_load_init_file=0 c_mem_type=1 c_mux_pipeline_stages=0 c_prim_type=1
c_read_depth_a=512 c_read_depth_b=512 c_read_latency_a=1 c_read_latency_b=1
c_read_width_a=8 c_read_width_b=8 c_rst_priority_a=CE c_rst_priority_b=CE
c_rstram_a=0 c_rstram_b=0 c_sim_collision_check=ALL c_use_bram_block=0
c_use_byte_wea=0 c_use_byte_web=0 c_use_default_data=0 c_use_ecc=0
c_use_softecc=0 c_use_uram=0 c_wea_width=1 c_web_width=1
c_write_depth_a=512 c_write_depth_b=512 c_write_mode_a=NO_CHANGE c_write_mode_b=READ_FIRST
c_write_width_a=8 c_write_width_b=8 c_xdevicefamily=artix7 core_container=false
iptotal=1 x_ipcorerevision=4 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=blk_mem_gen x_ipproduct=Vivado 2020.1 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=8.4
xadc_wiz_v3_3_8/1
channel_averaging=None component_name=xadc_wiz_0 core_container=false dclk_frequency=100
enable_axi=false enable_axi4stream=false enable_busy=true enable_convst=false
enable_convstclk=false enable_dclk=true enable_drp=true enable_eoc=true
enable_eos=true enable_vbram_alaram=false enable_vccaux_alaram=true enable_vccddro_alaram=false
enable_vccint_alaram=false enable_vccpaux_alaram=false enable_vccpint_alaram=false iptotal=1
ot_alaram=false sequencer_mode=on startup_channel_selection=contineous_sequence timing_mode=continuous
user_temp_alaram=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1 dpip-1=1 dpop-1=1 dpop-2=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-17=301

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") bram=0.300797 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.175977
die=xc7a200tsbg484-1 dsp=0.997788 dsp_output_toggle=12.500000 dynamic=5.157044
effective_thetaja=3.31 enable_probability=0.990000 family=artix7 ff_toggle=12.500000
flow_state=routed heatsink=medium (Medium Profile) i/o=1.440817 input_toggle=12.500000
junction_temp=42.7 (C) logic=1.126557 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=5.333020 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=sbg484 pct_clock_constrained=3.000000 pct_inputs_defined=0 platform=nt64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=1.169835 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=5.0 (C/W)
thetasa=4.6 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=3.31
user_junc_temp=42.7 (C) user_thetajb=5.0 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.050000
vccadc_static_current=0.020000 vccadc_total_current=0.070000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.051478
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.034030 vccaux_total_current=0.085508 vccaux_voltage=1.800000 vccbram_dynamic_current=0.016734
vccbram_static_current=0.001554 vccbram_total_current=0.018288 vccbram_voltage=1.000000 vccint_dynamic_current=3.645493
vccint_static_current=0.060669 vccint_total_current=3.706162 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.397623
vcco33_static_current=0.005000 vcco33_total_current=0.402623 vcco33_voltage=3.300000 version=2020.1
xadc=0.121250

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=120 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=40 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=20 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=40 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=10 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=10 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=1 dsps_available=740 dsps_fixed=0 dsps_used=1
dsps_util_percentage=0.14
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=1 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=365 block_ram_tile_fixed=0 block_ram_tile_used=1.5 block_ram_tile_util_percentage=0.41
ramb18_available=730 ramb18_fixed=0 ramb18_used=3 ramb18_util_percentage=0.41
ramb18e1_only_used=3 ramb36_fifo_available=365 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=12
dsp48e1_functional_category=Block Arithmetic dsp48e1_used=1 fdre_functional_category=Flop & Latch fdre_used=287
fdse_functional_category=Flop & Latch fdse_used=8 ibuf_functional_category=IO ibuf_used=10
lut1_functional_category=LUT lut1_used=6 lut2_functional_category=LUT lut2_used=42
lut3_functional_category=LUT lut3_used=42 lut4_functional_category=LUT lut4_used=49
lut5_functional_category=LUT lut5_used=56 lut6_functional_category=LUT lut6_used=123
muxf7_functional_category=MuxFx muxf7_used=6 obuf_functional_category=IO obuf_used=6
ramb18e1_functional_category=Block Memory ramb18e1_used=3 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=66900 f7_muxes_fixed=0 f7_muxes_used=6 f7_muxes_util_percentage=<0.01
f8_muxes_available=33450 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=133800 lut_as_logic_fixed=0 lut_as_logic_used=258 lut_as_logic_util_percentage=0.19
lut_as_memory_available=46200 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=267600 register_as_flip_flop_fixed=0 register_as_flip_flop_used=295 register_as_flip_flop_util_percentage=0.11
register_as_latch_available=267600 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=133800 slice_luts_fixed=0 slice_luts_used=258 slice_luts_util_percentage=0.19
slice_registers_available=267600 slice_registers_fixed=0 slice_registers_used=295 slice_registers_util_percentage=0.11
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=133800 lut_as_logic_fixed=0
lut_as_logic_used=258 lut_as_logic_util_percentage=0.19 lut_as_memory_available=46200 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=87 lut_in_front_of_the_register_is_used_fixed=87 lut_in_front_of_the_register_is_used_used=47
register_driven_from_outside_the_slice_fixed=47 register_driven_from_outside_the_slice_used=134 register_driven_from_within_the_slice_fixed=134 register_driven_from_within_the_slice_used=161
slice_available=33450 slice_fixed=0 slice_registers_available=267600 slice_registers_fixed=0
slice_registers_used=295 slice_registers_util_percentage=0.11 slice_used=108 slice_util_percentage=0.32
slicel_fixed=0 slicel_used=67 slicem_fixed=0 slicem_used=41
unique_control_sets_available=33450 unique_control_sets_fixed=33450 unique_control_sets_used=31 unique_control_sets_util_percentage=0.09
using_o5_and_o6_fixed=0.09 using_o5_and_o6_used=60 using_o5_output_only_fixed=60 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=198
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=1 xadc_used=1 xadc_util_percentage=100.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=RuntimeOptimized -fanout_limit=default::10000
-flatten_hierarchy=none -fsm_extraction=off -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7a200tsbg484-1 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=top -verilog_define=default::[not_specified]
usage
elapsed=00:00:53s hls_ip=0 memory_gain=283.348MB memory_peak=1363.926MB