Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version2902540
date_generatedThu Nov 5 13:33:15 2020 os_platformLIN64
product_versionVivado v2020.1 (64-bit) project_id4c2642c387de4b1d9342deba179e58db
project_iteration1 random_idae3ff47605875caa853e2d43cee63b98
registration_idae3ff47605875caa853e2d43cee63b98 route_designTRUE
target_devicexc7s50 target_familyspartan7
target_packagecsga324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-10750H CPU @ 2.60GHz cpu_speed3151.560 MHz
os_nameKali os_releaseKali GNU/Linux Rolling
system_ram16.000 GB total_processors1

vivado_usage
other_data
tclmode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=2 totalsynthesisruns=2

unisim_transformation
post_unisim_transformation
bufg=1 fdre=11 gnd=2 ibuf=23
lut2=3 lut3=3 lut4=4 obuf=6
vcc=1 xadc=1
pre_unisim_transformation
bufg=1 fdre=11 gnd=2 ibuf=23
lut2=3 lut3=3 lut4=4 obuf=6
vcc=1 xadc=1

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

ip_statistics
xadc_wiz_v3_3_8/1
channel_averaging=None component_name=xadc_wiz_0 core_container=false dclk_frequency=100
enable_axi=false enable_axi4stream=false enable_busy=true enable_convst=false
enable_convstclk=false enable_dclk=true enable_drp=true enable_eoc=true
enable_eos=true enable_vbram_alaram=false enable_vccaux_alaram=true enable_vccddro_alaram=false
enable_vccint_alaram=true enable_vccpaux_alaram=false enable_vccpint_alaram=false iptotal=1
ot_alaram=false sequencer_mode=on startup_channel_selection=contineous_sequence timing_mode=continuous
user_temp_alaram=false

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-slack_lesser_than=default::[not_specified] -waived=default::[not_specified]
results
timing-18=10

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -hierarchical_depth=default::4 -l=default::[not_specified] -name=default::[not_specified]
-no_propagation=default::[not_specified] -return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified]
-vid=default::[not_specified] -xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=12to15 (12 to 15 Layers) board_selection=medium (10"x10") clocks=0.000438 confidence_level_clock_activity=High
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=Low
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.071708
die=xc7s50csga324-1 dsp_output_toggle=12.500000 dynamic=0.003940 effective_thetaja=4.94
enable_probability=0.990000 family=spartan7 ff_toggle=12.500000 flow_state=routed
heatsink=medium (Medium Profile) i/o=0.001490 input_toggle=12.500000 junction_temp=25.4 (C)
logic=0.000024 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.075648
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=csga324
pct_clock_constrained=0.460000 pct_inputs_defined=4 platform=lin64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.000049 simulation_file=None speedgrade=-1
static_prob=False temp_grade=commercial thetajb=7.6 (C/W) thetasa=4.6 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=4.94 user_junc_temp=25.4 (C)
user_thetajb=7.6 (C/W) user_thetasa=4.6 (C/W) vccadc_dynamic_current=0.000800 vccadc_static_current=0.020000
vccadc_total_current=0.020800 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000090 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.012615
vccaux_total_current=0.012705 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000161
vccbram_total_current=0.000161 vccbram_voltage=1.000000 vccint_dynamic_current=0.001341 vccint_static_current=0.009540
vccint_total_current=0.010881 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000302 vcco33_static_current=0.001000
vcco33_total_current=0.001302 vcco33_voltage=3.300000 version=2020.1 xadc=0.001940

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=20 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=10 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=20 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=5 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=5 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=120 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=1 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=75 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=150 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=75 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=1 fdre_functional_category=Flop & Latch fdre_used=11
ibuf_functional_category=IO ibuf_used=23 lut2_functional_category=LUT lut2_used=3
lut3_functional_category=LUT lut3_used=3 lut4_functional_category=LUT lut4_used=4
obuf_functional_category=IO obuf_used=6 xadc_functional_category=Others xadc_used=1
slice_logic
f7_muxes_available=16300 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=8150 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=32600 lut_as_logic_fixed=0 lut_as_logic_used=6 lut_as_logic_util_percentage=0.02
lut_as_memory_available=9600 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=65200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=11 register_as_flip_flop_util_percentage=0.02
register_as_latch_available=65200 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=32600 slice_luts_fixed=0 slice_luts_used=6 slice_luts_util_percentage=0.02
slice_registers_available=65200 slice_registers_fixed=0 slice_registers_used=11 slice_registers_util_percentage=0.02
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0 lut_as_logic_available=32600 lut_as_logic_fixed=0
lut_as_logic_used=6 lut_as_logic_util_percentage=0.02 lut_as_memory_available=9600 lut_as_memory_fixed=0
lut_as_memory_used=0 lut_as_memory_util_percentage=0.00 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=0 lut_in_front_of_the_register_is_used_fixed=0 lut_in_front_of_the_register_is_used_used=2
register_driven_from_outside_the_slice_fixed=2 register_driven_from_outside_the_slice_used=2 register_driven_from_within_the_slice_fixed=2 register_driven_from_within_the_slice_used=9
slice_available=8150 slice_fixed=0 slice_registers_available=65200 slice_registers_fixed=0
slice_registers_used=11 slice_registers_util_percentage=0.02 slice_used=3 slice_util_percentage=0.04
slicel_fixed=0 slicel_used=3 slicem_fixed=0 slicem_used=0
unique_control_sets_available=8150 unique_control_sets_fixed=8150 unique_control_sets_used=2 unique_control_sets_util_percentage=0.02
using_o5_and_o6_fixed=0.02 using_o5_and_o6_used=4 using_o5_output_only_fixed=4 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=2
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=1 xadc_used=1 xadc_util_percentage=100.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -debug_log=default::[not_specified] -directive=RuntimeOptimized -fanout_limit=default::10000
-flatten_hierarchy=none -fsm_extraction=off -gated_clock_conversion=default::off -generic=default::[not_specified]
-include_dirs=default::[not_specified] -keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1
-max_dsp=default::-1 -max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default
-name=default::[not_specified] -no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified]
-part=xc7s50csga324-1 -resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified]
-rtl_skip_constraints=default::[not_specified] -rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified]
-shreg_min_size=default::3 -top=XADCdemo -verilog_define=default::[not_specified]
usage
elapsed=00:00:14s hls_ip=0 memory_gain=173.594MB memory_peak=2289.137MB