TABLE OF CONTENTS

Overview
Block Diagram
External Ports
Processor
   microblaze_0
Debuggers
   mdm_0
Busses
   dlmb
   ilmb
   mb_plb
Memory
   lmb_bram
Memory Controllers
   dlmb_cntlr
   ilmb_cntlr
Peripherals
   LED_7SEGMENT
   LEDs_8Bit
   Push_Buttons_3Bit
   RS232_PORT
   Switches_8Bit
IP
   chipscope_icon_0
   chipscope_vio_0
   clock_generator_0
   proc_sys_reset_0
Timing Information
Overview TOC
Resources Used
1   MicroBlaze
1   Processor Local Bus (PLB) 4.6
2   Local Memory Bus (LMB) 1.0
1   Block RAM (BRAM) Block
2   LMB BRAM Controller
4   XPS General Purpose IO
1   XPS UART (Lite)
1   Clock Generator
1   MicroBlaze Debug Module (MDM)
1   Processor System Reset Module
1   Chipscope Virtual IO (VIO)
1   Chipscope Integrated Controller
Specifics
Generated Thu Jun 24 16:56:08 2010
EDK Version 12.1
Device Family spartan3e
Device xc3s500efg320-4

Block Diagram TOC

BlockDiagram
External Ports TOC

These are the external ports defined in the MHS file.
Attributes Key
The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file
CLK  indicates Clock ports, (SIGIS = CLK) 
INTR  indicates Interrupt ports,(SIGIS = INTR) 
RESET  indicates Reset ports, (SIGIS = RST) 
BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) 
# NAME DIR [LSB:MSB] SIG ATTRIBUTES
LED_7SEGMENT fpga_0_LED_7SEGMENT_GPIO_IO_O_pin O 0:11 fpga_0_LED_7SEGMENT_GPIO_IO_O_pin
RS232_PORT fpga_0_RS232_PORT_RX_pin I 1 fpga_0_RS232_PORT_RX_pin
RS232_PORT fpga_0_RS232_PORT_TX_pin O 1 fpga_0_RS232_PORT_TX_pin
Switches_8Bit fpga_0_Switches_8Bit_GPIO_IO_I_pin I 0:7 fpga_0_Switches_8Bit_GPIO_IO_I_pin
chipscope_vio_0 fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin I 0:2 fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin_to_chipscope_vio_0
chipscope_vio_0 fpga_0_LEDs_8Bit_GPIO_IO_O_pin O 0:7 fpga_0_LEDs_8Bit_GPIO_IO_O_pin_to_chipscope_vio_0
clock_generator_0 fpga_0_clk_1_sys_clk_pin I 1 dcm_clk_s  CLK 
proc_sys_reset_0 fpga_0_rst_1_sys_rst_pin I 1 sys_rst_s  RESET 


Processors TOC

microblaze_0   MicroBlaze
The MicroBlaze 32 bit soft processor

IP Specs
Core Version Documentation
microblaze 7.30.a IP


microblaze_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 MB_RESET I 1 mb_reset
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
DLMB MASTER LMB dlmb dlmb_cntlr
ILMB MASTER LMB ilmb ilmb_cntlr
DPLB MASTER PLBV46 mb_plb 6 Peripherals.
IPLB MASTER PLBV46 mb_plb 6 Peripherals.
DEBUG TARGET XIL_MBDEBUG2 microblaze_0_mdm_bus mdm_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SCO 0
C_FREQ 0
C_DATA_SIZE 32
C_DYNAMIC_BUS_SIZING 1
C_FAMILY spartan3e
C_INSTANCE microblaze
C_AREA_OPTIMIZED 1
C_OPTIMIZATION 0
C_INTERCONNECT 1
C_DPLB_DWIDTH 32
C_DPLB_NATIVE_DWIDTH 32
C_DPLB_BURST_EN 0
C_DPLB_P2P 0
C_IPLB_DWIDTH 32
C_IPLB_NATIVE_DWIDTH 32
C_IPLB_BURST_EN 0
C_IPLB_P2P 0
C_D_PLB 0
C_D_LMB 1
C_I_PLB 0
C_I_LMB 1
C_USE_MSR_INSTR 1
C_USE_PCMP_INSTR 1
C_USE_BARREL 0
C_USE_DIV 0
C_USE_HW_MUL 1
C_USE_FPU 0
C_UNALIGNED_EXCEPTIONS 0
C_ILL_OPCODE_EXCEPTION 0
C_IPLB_BUS_EXCEPTION 0
C_DPLB_BUS_EXCEPTION 0
C_DIV_ZERO_EXCEPTION 0
C_FPU_EXCEPTION 0
C_FSL_EXCEPTION 0
C_PVR 0
C_PVR_USER1 0x00
C_PVR_USER2 0x00000000
C_DEBUG_ENABLED 1
C_NUMBER_OF_PC_BRK 1
C_NUMBER_OF_RD_ADDR_BRK 0
C_NUMBER_OF_WR_ADDR_BRK 0
 
Name Value
C_INTERRUPT_IS_EDGE 0
C_EDGE_IS_POSITIVE 1
C_RESET_MSR 0x00000000
C_OPCODE_0x0_ILLEGAL 0
C_FSL_LINKS 0
C_FSL_DATA_SIZE 32
C_USE_EXTENDED_FSL_INSTR 0
C_ICACHE_BASEADDR 0x00000000
C_ICACHE_HIGHADDR 0x3FFFFFFF
C_USE_ICACHE 0
C_ALLOW_ICACHE_WR 1
C_ADDR_TAG_BITS 17
C_CACHE_BYTE_SIZE 8192
C_ICACHE_USE_FSL 1
C_ICACHE_LINE_LEN 4
C_ICACHE_ALWAYS_USED 0
C_ICACHE_INTERFACE 0
C_ICACHE_VICTIMS 0
C_ICACHE_STREAMS 0
C_DCACHE_BASEADDR 0x00000000
C_DCACHE_HIGHADDR 0x3FFFFFFF
C_USE_DCACHE 0
C_ALLOW_DCACHE_WR 1
C_DCACHE_ADDR_TAG 17
C_DCACHE_BYTE_SIZE 8192
C_DCACHE_USE_FSL 1
C_DCACHE_LINE_LEN 4
C_DCACHE_ALWAYS_USED 0
C_DCACHE_INTERFACE 0
C_DCACHE_USE_WRITEBACK 0
C_DCACHE_VICTIMS 0
C_USE_MMU 0
C_MMU_DTLB_SIZE 4
C_MMU_ITLB_SIZE 2
C_MMU_TLB_ACCESS 3
C_MMU_ZONES 16
C_USE_INTERRUPT 0
C_USE_EXT_BRK 0
C_USE_EXT_NM_BRK 0
C_USE_BRANCH_TARGET_CACHE 0
C_BRANCH_TARGET_CACHE_SIZE 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Debuggers TOC

mdm_0   MicroBlaze Debug Module (MDM)
Debug module for MicroBlaze Soft Processor.

IP Specs
Core Version Documentation
mdm 1.00.g IP


mdm_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Debug_SYS_Rst O 1 Debug_SYS_Rst
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
MBDEBUG_0 INITIATOR XIL_MBDEBUG2 microblaze_0_mdm_bus microblaze_0
SPLB SLAVE PLBV46 mb_plb 6 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex6
C_JTAG_CHAIN 2
C_INTERCONNECT 1
C_BASEADDR 0x84400000
C_HIGHADDR 0x8440ffff
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 3
 
Name Value
C_SPLB_NUM_MASTERS 8
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_OPB_DWIDTH 32
C_OPB_AWIDTH 32
C_MB_DBG_PORTS 1
C_USE_UART 1
C_UART_WIDTH 8
C_WRITE_FSL_PORTS 0
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Busses TOC

dlmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 1.00.a IP


dlmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LMB_Clk I 1 clk_50_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DLMB
dlmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ilmb   Local Memory Bus (LMB) 1.0
'The LMB is a fast, local bus for connecting MicroBlaze I and D ports to peripherals and BRAM'

IP Specs
Core Version Documentation
lmb_v10 1.00.a IP


ilmb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 LMB_Clk I 1 clk_50_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER ILMB
ilmb_cntlr SLAVE SLMB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_LMB_NUM_SLAVES 4
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
C_EXT_RESET_HIGH 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


mb_plb   Processor Local Bus (PLB) 4.6
'Xilinx 64-bit Processor Local Bus (PLB) consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units with a a three-cycle only arbitration feature'

IP Specs
Core Version Documentation
plb_v46 1.04.a IP


mb_plb IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 PLB_Clk I 1 clk_50_0000MHz
1 SYS_Rst I 1 sys_bus_reset
Bus Connections
INSTANCE INTERFACE TYPE INTERFACE NAME
microblaze_0 MASTER DPLB
microblaze_0 MASTER IPLB
LEDs_8Bit SLAVE SPLB
LED_7SEGMENT SLAVE SPLB
Push_Buttons_3Bit SLAVE SPLB
Switches_8Bit SLAVE SPLB
RS232_PORT SLAVE SPLB
mdm_0 SLAVE SPLB


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_PLBV46_NUM_MASTERS 4
C_PLBV46_NUM_SLAVES 8
C_PLBV46_MID_WIDTH 2
C_PLBV46_AWIDTH 32
C_PLBV46_DWIDTH 64
C_DCR_INTFCE 0
C_BASEADDR 0b1111111111
C_HIGHADDR 0b0000000000
C_DCR_AWIDTH 10
 
Name Value
C_DCR_DWIDTH 32
C_EXT_RESET_HIGH 1
C_IRQ_ACTIVE 1
C_NUM_CLK_PLB2OPB_REARB 5
C_ADDR_PIPELINING_TYPE 1
C_FAMILY spartan3e
C_P2P 0
C_ARB_TYPE 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memorys TOC

lmb_bram   Block RAM (BRAM) Block
The BRAM Block is a configurable memory module that attaches to a variety of BRAM Interface Controllers.

IP Specs
Core Version Documentation
bram_block 1.00.a IP


lmb_bram IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
PORTA TARGET XIL_BRAM ilmb_port ilmb_cntlr
PORTB TARGET XIL_BRAM dlmb_port dlmb_cntlr


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_MEMSIZE 2048
C_PORT_DWIDTH 32
C_PORT_AWIDTH 32
C_NUM_WE 4
C_FAMILY spartan3e
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Memory Controllers TOC

dlmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 2.10.b IP


dlmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM dlmb_port lmb_bram
SLMB SLAVE LMB dlmb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00003fff
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


ilmb_cntlr   LMB BRAM Controller
Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller connects to an lmb bus

IP Specs
Core Version Documentation
lmb_bram_if_cntlr 2.10.b IP


ilmb_cntlr IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
BRAM_PORT INITIATOR XIL_BRAM ilmb_port lmb_bram
SLMB SLAVE LMB ilmb microblaze_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x00000000
C_HIGHADDR 0x00003fff
C_MASK 0x00800000
C_LMB_AWIDTH 32
C_LMB_DWIDTH 32
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Peripherals TOC

LED_7SEGMENT   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP


LED_7SEGMENT IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 GPIO_IO_O O 1 fpga_0_LED_7SEGMENT_GPIO_IO_O_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 6 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x81460000
C_HIGHADDR 0x8146ffff
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_FAMILY spartan3e
 
Name Value
C_ALL_INPUTS 0
C_ALL_INPUTS_2 0
C_GPIO_WIDTH 12
C_GPIO2_WIDTH 32
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xffffffff
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xffffffff
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


LEDs_8Bit   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP


LEDs_8Bit IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 GPIO_IO_O O 1 fpga_0_LEDs_8Bit_GPIO_IO_O_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 6 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x81440000
C_HIGHADDR 0x8144ffff
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_FAMILY spartan3e
 
Name Value
C_ALL_INPUTS 0
C_ALL_INPUTS_2 0
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xffffffff
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xffffffff
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


Push_Buttons_3Bit   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP


Push_Buttons_3Bit IP Image
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 6 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x81420000
C_HIGHADDR 0x8142ffff
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_FAMILY spartan3e
 
Name Value
C_ALL_INPUTS 1
C_ALL_INPUTS_2 0
C_GPIO_WIDTH 3
C_GPIO2_WIDTH 32
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xffffffff
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xffffffff
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


RS232_PORT   XPS UART (Lite)
Generic UART (Universal Asynchronous Receiver/Transmitter) for PLBV46 bus.

IP Specs
Core Version Documentation
xps_uartlite 1.01.a IP


RS232_PORT IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 RX I 1 fpga_0_RS232_PORT_RX_pin
1 TX O 1 fpga_0_RS232_PORT_TX_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 6 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY spartan3e
C_SPLB_CLK_FREQ_HZ 100000000
C_BASEADDR 0x84000000
C_HIGHADDR 0x8400ffff
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
 
Name Value
C_SPLB_NUM_MASTERS 1
C_SPLB_SUPPORT_BURSTS 0
C_SPLB_NATIVE_DWIDTH 32
C_BAUDRATE 9600
C_DATA_BITS 8
C_USE_PARITY 0
C_ODD_PARITY 0
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


Switches_8Bit   XPS General Purpose IO
General Purpose Input/Output (GPIO) core for the PLBV46 bus.

IP Specs
Core Version Documentation
xps_gpio 2.00.a IP


Switches_8Bit IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 GPIO_IO_I I 1 fpga_0_Switches_8Bit_GPIO_IO_I_pin
Bus Interfaces
 NAME   TYPE  BUSSTD BUS Connected To
SPLB SLAVE PLBV46 mb_plb 6 Peripherals.


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_BASEADDR 0x81400000
C_HIGHADDR 0x8140ffff
C_SPLB_AWIDTH 32
C_SPLB_DWIDTH 32
C_SPLB_P2P 0
C_SPLB_MID_WIDTH 1
C_SPLB_NUM_MASTERS 1
C_SPLB_NATIVE_DWIDTH 32
C_SPLB_SUPPORT_BURSTS 0
C_FAMILY spartan3e
 
Name Value
C_ALL_INPUTS 1
C_ALL_INPUTS_2 0
C_GPIO_WIDTH 8
C_GPIO2_WIDTH 32
C_INTERRUPT_PRESENT 0
C_DOUT_DEFAULT 0x00000000
C_TRI_DEFAULT 0xffffffff
C_IS_DUAL 0
C_DOUT_DEFAULT_2 0x00000000
C_TRI_DEFAULT_2 0xffffffff
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




IP TOC

chipscope_icon_0   Chipscope Integrated Controller
'The Chipscope ICON core provides a communication path between the FPGA Boundary Scan port and the other Chipscope Cores OPB IBA, PLB IBA, VIO, and the ILA.'

IP Specs
Core Version Documentation
chipscope_icon 1.04.a IP


chipscope_icon_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 control0 O 1 chipscope_vio_0_icon_control


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_DEVICE xc5vlx50
C_PACKAGE ffg676
C_SPEEDGRADE -11
C_NUM_CONTROL_PORTS 1
C_SYSTEM_CONTAINS_MDM 0
C_FORCE_BSCAN_USER_PORT 1
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


chipscope_vio_0   Chipscope Virtual IO (VIO)
Chipscope VIO (Virtual IO) core both monitors and drives internal FPGA signals in real time.

IP Specs
Core Version Documentation
chipscope_vio 1.03.a IP


chipscope_vio_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 chipscope_icon_control I 1 chipscope_vio_0_icon_control
1 async_out O 1 fpga_0_LEDs_8Bit_GPIO_IO_O_pin_to_chipscope_vio_0
2 async_in I 1 fpga_0_Push_Buttons_3Bit_GPIO_IO_I_pin_to_chipscope_vio_0


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex2
C_DEVICE xc4vfx12
C_PACKAGE ff1016
C_SPEEDGRADE -11
C_ASYNC_INPUT_ENABLE 1
C_ASYNC_INPUT_WIDTH 3
C_ASYNC_OUTPUT_ENABLE 1
 
Name Value
C_ASYNC_OUTPUT_WIDTH 8
C_SYNC_INPUT_ENABLE 0
C_SYNC_INPUT_WIDTH 8
C_SYNC_OUTPUT_ENABLE 0
C_SYNC_OUTPUT_WIDTH 8
C_RISING_CLOCK_EDGE 1
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


clock_generator_0   Clock Generator
Clock generator for processor system.

IP Specs
Core Version Documentation
clock_generator 3.02.a IP


clock_generator_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 CLKIN I 1 dcm_clk_s
1 CLKOUT0 O 1 clk_50_0000MHz
2 RST I 1 net_gnd
3 LOCKED O 1 Dcm_all_locked


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_FAMILY virtex5
C_SPEEDGRADE 0
C_EXT_RESET_HIGH 1
C_CLK_GEN update
C_CLKOUT0_MODULE NONE
C_CLKOUT0_PORT NONE
C_CLKOUT1_MODULE NONE
C_CLKOUT1_PORT NONE
C_CLKOUT2_MODULE NONE
C_CLKOUT2_PORT NONE
C_CLKOUT3_MODULE NONE
C_CLKOUT3_PORT NONE
C_CLKOUT4_MODULE NONE
C_CLKOUT4_PORT NONE
C_CLKOUT5_MODULE NONE
C_CLKOUT5_PORT NONE
C_CLKOUT6_MODULE NONE
C_CLKOUT6_PORT NONE
C_CLKOUT7_MODULE NONE
C_CLKOUT7_PORT NONE
C_CLKOUT8_MODULE NONE
C_CLKOUT8_PORT NONE
C_CLKOUT9_MODULE NONE
C_CLKOUT9_PORT NONE
C_CLKOUT10_MODULE NONE
C_CLKOUT10_PORT NONE
C_CLKOUT11_MODULE NONE
C_CLKOUT11_PORT NONE
C_CLKOUT12_MODULE NONE
C_CLKOUT12_PORT NONE
C_CLKOUT13_MODULE NONE
C_CLKOUT13_PORT NONE
C_CLKOUT14_MODULE NONE
C_CLKOUT14_PORT NONE
C_CLKOUT15_MODULE NONE
C_CLKOUT15_PORT NONE
C_CLKFBOUT_MODULE NONE
C_CLKFBOUT_PORT NONE
C_PSDONE_MODULE NONE
C_PLL0_DIVCLK_DIVIDE 1
C_PLL0_CLKFBOUT_MULT 1
C_PLL0_CLKFBOUT_PHASE 0.000000
C_PLL0_CLKIN1_PERIOD 0.000000
C_PLL0_CLKOUT0_DIVIDE 1
C_PLL0_CLKOUT0_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT0_PHASE 0.000000
C_PLL0_CLKOUT1_DIVIDE 1
C_PLL0_CLKOUT1_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT1_PHASE 0.000000
C_PLL0_CLKOUT2_DIVIDE 1
C_PLL0_CLKOUT2_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT2_PHASE 0.000000
C_PLL0_CLKOUT3_DIVIDE 1
C_PLL0_CLKOUT3_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT3_PHASE 0.000000
C_PLL0_CLKOUT4_DIVIDE 1
C_PLL0_CLKOUT4_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT4_PHASE 0.000000
C_PLL0_CLKOUT5_DIVIDE 1
C_PLL0_CLKOUT5_DUTY_CYCLE 0.500000
C_PLL0_CLKOUT5_PHASE 0.000000
C_PLL0_BANDWIDTH OPTIMIZED
C_PLL0_COMPENSATION SYSTEM_SYNCHRONOUS
C_PLL0_REF_JITTER 0.100000
C_PLL0_RESET_ON_LOSS_OF_LOCK false
C_PLL0_RST_DEASSERT_CLK CLKIN1
C_PLL0_EXT_RESET_HIGH 1
C_PLL0_FAMILY virtex5
C_PLL0_CLKOUT0_DESKEW_ADJUST NONE
C_PLL0_CLKOUT1_DESKEW_ADJUST NONE
C_PLL0_CLKOUT2_DESKEW_ADJUST NONE
C_PLL0_CLKOUT3_DESKEW_ADJUST NONE
C_PLL0_CLKOUT4_DESKEW_ADJUST NONE
C_PLL0_CLKOUT5_DESKEW_ADJUST NONE
C_PLL0_CLKFBOUT_DESKEW_ADJUST NONE
C_PLL0_CLKIN1_BUF false
C_PLL0_CLKFBOUT_BUF false
C_PLL0_CLKOUT0_BUF false
C_PLL0_CLKOUT1_BUF false
C_PLL0_CLKOUT2_BUF false
C_PLL0_CLKOUT3_BUF false
C_PLL0_CLKOUT4_BUF false
C_PLL0_CLKOUT5_BUF false
C_PLL0_CLKIN1_MODULE NONE
C_PLL0_CLKIN1_PORT NONE
C_PLL0_CLKFBIN_MODULE NONE
C_PLL0_CLKFBIN_PORT NONE
C_PLL0_RST_MODULE NONE
C_PLL1_DIVCLK_DIVIDE 1
C_PLL1_CLKFBOUT_MULT 1
C_PLL1_CLKFBOUT_PHASE 0.000000
C_PLL1_CLKIN1_PERIOD 0.000000
C_PLL1_CLKOUT0_DIVIDE 1
C_PLL1_CLKOUT0_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT0_PHASE 0.000000
C_PLL1_CLKOUT1_DIVIDE 1
C_PLL1_CLKOUT1_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT1_PHASE 0.000000
C_PLL1_CLKOUT2_DIVIDE 1
C_PLL1_CLKOUT2_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT2_PHASE 0.000000
C_PLL1_CLKOUT3_DIVIDE 1
C_PLL1_CLKOUT3_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT3_PHASE 0.000000
C_PLL1_CLKOUT4_DIVIDE 1
C_PLL1_CLKOUT4_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT4_PHASE 0.000000
C_PLL1_CLKOUT5_DIVIDE 1
C_PLL1_CLKOUT5_DUTY_CYCLE 0.500000
C_PLL1_CLKOUT5_PHASE 0.000000
C_PLL1_BANDWIDTH OPTIMIZED
C_PLL1_COMPENSATION SYSTEM_SYNCHRONOUS
C_PLL1_REF_JITTER 0.100000
C_PLL1_RESET_ON_LOSS_OF_LOCK false
C_PLL1_RST_DEASSERT_CLK CLKIN1
C_PLL1_EXT_RESET_HIGH 1
C_PLL1_FAMILY virtex5
C_PLL1_CLKOUT0_DESKEW_ADJUST NONE
C_PLL1_CLKOUT1_DESKEW_ADJUST NONE
C_PLL1_CLKOUT2_DESKEW_ADJUST NONE
C_PLL1_CLKOUT3_DESKEW_ADJUST NONE
C_PLL1_CLKOUT4_DESKEW_ADJUST NONE
C_PLL1_CLKOUT5_DESKEW_ADJUST NONE
C_PLL1_CLKFBOUT_DESKEW_ADJUST NONE
C_PLL1_CLKIN1_BUF false
C_PLL1_CLKFBOUT_BUF false
C_PLL1_CLKOUT0_BUF false
C_PLL1_CLKOUT1_BUF false
C_PLL1_CLKOUT2_BUF false
C_PLL1_CLKOUT3_BUF false
C_PLL1_CLKOUT4_BUF false
C_PLL1_CLKOUT5_BUF false
C_PLL1_CLKIN1_MODULE NONE
C_PLL1_CLKIN1_PORT NONE
C_PLL1_CLKFBIN_MODULE NONE
C_PLL1_CLKFBIN_PORT NONE
C_PLL1_RST_MODULE NONE
C_DCM0_DFS_FREQUENCY_MODE LOW
C_DCM0_DLL_FREQUENCY_MODE LOW
C_DCM0_DUTY_CYCLE_CORRECTION true
C_DCM0_CLKIN_DIVIDE_BY_2 false
C_DCM0_CLK_FEEDBACK 1X
C_DCM0_CLKOUT_PHASE_SHIFT NONE
C_DCM0_DSS_MODE NONE
C_DCM0_STARTUP_WAIT false
C_DCM0_PHASE_SHIFT 0
C_DCM0_CLKFX_MULTIPLY 4
C_DCM0_CLKFX_DIVIDE 1
C_DCM0_CLKDV_DIVIDE 2.000000
C_DCM0_CLKIN_PERIOD 0.000000
C_DCM0_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM0_CLKIN_BUF false
C_DCM0_CLKFB_BUF false
C_DCM0_CLK0_BUF false
C_DCM0_CLK90_BUF false
C_DCM0_CLK180_BUF false
C_DCM0_CLK270_BUF false
C_DCM0_CLKDV_BUF false
C_DCM0_CLKDV180_BUF false
C_DCM0_CLK2X_BUF false
C_DCM0_CLK2X180_BUF false
C_DCM0_CLKFX_BUF false
C_DCM0_CLKFX180_BUF false
C_DCM0_EXT_RESET_HIGH 1
C_DCM0_FAMILY virtex5
C_DCM0_CLKIN_MODULE NONE
C_DCM0_CLKIN_PORT NONE
C_DCM0_CLKFB_MODULE NONE
C_DCM0_CLKFB_PORT NONE
C_DCM0_RST_MODULE NONE
C_DCM1_DFS_FREQUENCY_MODE LOW
C_DCM1_DLL_FREQUENCY_MODE LOW
C_DCM1_DUTY_CYCLE_CORRECTION true
C_DCM1_CLKIN_DIVIDE_BY_2 false
C_DCM1_CLK_FEEDBACK 1X
C_DCM1_CLKOUT_PHASE_SHIFT NONE
C_DCM1_DSS_MODE NONE
C_DCM1_STARTUP_WAIT false
C_DCM1_PHASE_SHIFT 0
C_DCM1_CLKFX_MULTIPLY 4
C_DCM1_CLKFX_DIVIDE 1
C_DCM1_CLKDV_DIVIDE 2.000000
C_DCM1_CLKIN_PERIOD 0.000000
C_DCM1_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM1_CLKIN_BUF false
C_DCM1_CLKFB_BUF false
C_DCM1_CLK0_BUF false
C_DCM1_CLK90_BUF false
C_DCM1_CLK180_BUF false
C_DCM1_CLK270_BUF false
C_DCM1_CLKDV_BUF false
C_DCM1_CLKDV180_BUF false
C_DCM1_CLK2X_BUF false
C_DCM1_CLK2X180_BUF false
C_DCM1_CLKFX_BUF false
C_DCM1_CLKFX180_BUF false
C_DCM1_EXT_RESET_HIGH 1
C_DCM1_FAMILY virtex5
C_DCM1_CLKIN_MODULE NONE
C_DCM1_CLKIN_PORT NONE
C_DCM1_CLKFB_MODULE NONE
C_DCM1_CLKFB_PORT NONE
C_DCM1_RST_MODULE NONE
C_DCM2_DFS_FREQUENCY_MODE LOW
C_DCM2_DLL_FREQUENCY_MODE LOW
C_DCM2_DUTY_CYCLE_CORRECTION true
C_DCM2_CLKIN_DIVIDE_BY_2 false
C_DCM2_CLK_FEEDBACK 1X
C_DCM2_CLKOUT_PHASE_SHIFT NONE
C_DCM2_DSS_MODE NONE
C_DCM2_STARTUP_WAIT false
C_DCM2_PHASE_SHIFT 0
C_DCM2_CLKFX_MULTIPLY 4
C_DCM2_CLKFX_DIVIDE 1
C_DCM2_CLKDV_DIVIDE 2.000000
C_DCM2_CLKIN_PERIOD 0.000000
C_DCM2_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM2_CLKIN_BUF false
C_DCM2_CLKFB_BUF false
C_DCM2_CLK0_BUF false
C_DCM2_CLK90_BUF false
C_DCM2_CLK180_BUF false
C_DCM2_CLK270_BUF false
C_DCM2_CLKDV_BUF false
C_DCM2_CLKDV180_BUF false
C_DCM2_CLK2X_BUF false
C_DCM2_CLK2X180_BUF false
C_DCM2_CLKFX_BUF false
C_DCM2_CLKFX180_BUF false
C_DCM2_EXT_RESET_HIGH 1
C_DCM2_FAMILY virtex5
C_DCM2_CLKIN_MODULE NONE
C_DCM2_CLKIN_PORT NONE
C_DCM2_CLKFB_MODULE NONE
C_DCM2_CLKFB_PORT NONE
C_DCM2_RST_MODULE NONE
C_DCM3_DFS_FREQUENCY_MODE LOW
C_DCM3_DLL_FREQUENCY_MODE LOW
C_DCM3_DUTY_CYCLE_CORRECTION true
C_DCM3_CLKIN_DIVIDE_BY_2 false
C_DCM3_CLK_FEEDBACK 1X
C_DCM3_CLKOUT_PHASE_SHIFT NONE
C_DCM3_DSS_MODE NONE
C_DCM3_STARTUP_WAIT false
C_DCM3_PHASE_SHIFT 0
C_DCM3_CLKFX_MULTIPLY 4
C_DCM3_CLKFX_DIVIDE 1
C_DCM3_CLKDV_DIVIDE 2.000000
C_DCM3_CLKIN_PERIOD 0.000000
C_DCM3_DESKEW_ADJUST SYSTEM_SYNCHRONOUS
C_DCM3_CLKIN_BUF false
C_DCM3_CLKFB_BUF false
C_DCM3_CLK0_BUF false
C_DCM3_CLK90_BUF false
C_DCM3_CLK180_BUF false
C_DCM3_CLK270_BUF false
C_DCM3_CLKDV_BUF false
C_DCM3_CLKDV180_BUF false
C_DCM3_CLK2X_BUF false
C_DCM3_CLK2X180_BUF false
C_DCM3_CLKFX_BUF false
C_DCM3_CLKFX180_BUF false
C_DCM3_EXT_RESET_HIGH 1
C_DCM3_FAMILY virtex5
C_DCM3_CLKIN_MODULE NONE
C_DCM3_CLKIN_PORT NONE
C_DCM3_CLKFB_MODULE NONE
C_DCM3_CLKFB_PORT NONE
C_DCM3_RST_MODULE NONE
C_MMCM0_BANDWIDTH OPTIMIZED
C_MMCM0_CLKFBOUT_MULT_F 1.000000
C_MMCM0_CLKFBOUT_PHASE 0.000000
C_MMCM0_CLKFBOUT_USE_FINE_PS false
C_MMCM0_CLKIN1_PERIOD 0.000000
C_MMCM0_CLKOUT0_DIVIDE_F 1.000000
C_MMCM0_CLKOUT0_DUTY_CYCLE 0.500000
C_MMCM0_CLKOUT0_PHASE 0.000000
C_MMCM0_CLKOUT1_DIVIDE 1
C_MMCM0_CLKOUT1_DUTY_CYCLE 0.500000
C_MMCM0_CLKOUT1_PHASE 0.000000
C_MMCM0_CLKOUT2_DIVIDE 1
C_MMCM0_CLKOUT2_DUTY_CYCLE 0.500000
C_MMCM0_CLKOUT2_PHASE 0.000000
C_MMCM0_CLKOUT3_DIVIDE 1
C_MMCM0_CLKOUT3_DUTY_CYCLE 0.500000
C_MMCM0_CLKOUT3_PHASE 0.000000
C_MMCM0_CLKOUT4_DIVIDE 1
C_MMCM0_CLKOUT4_DUTY_CYCLE 0.500000
C_MMCM0_CLKOUT4_PHASE 0.000000
 
Name Value
C_MMCM0_CLKOUT4_CASCADE false
C_MMCM0_CLKOUT5_DIVIDE 1
C_MMCM0_CLKOUT5_DUTY_CYCLE 0.500000
C_MMCM0_CLKOUT5_PHASE 0.000000
C_MMCM0_CLKOUT6_DIVIDE 1
C_MMCM0_CLKOUT6_DUTY_CYCLE 0.500000
C_MMCM0_CLKOUT6_PHASE 0.000000
C_MMCM0_CLKOUT0_USE_FINE_PS false
C_MMCM0_CLKOUT1_USE_FINE_PS false
C_MMCM0_CLKOUT2_USE_FINE_PS false
C_MMCM0_CLKOUT3_USE_FINE_PS false
C_MMCM0_CLKOUT4_USE_FINE_PS false
C_MMCM0_CLKOUT5_USE_FINE_PS false
C_MMCM0_CLKOUT6_USE_FINE_PS false
C_MMCM0_COMPENSATION ZHOLD
C_MMCM0_DIVCLK_DIVIDE 1
C_MMCM0_REF_JITTER1 0.010000
C_MMCM0_CLKIN1_BUF false
C_MMCM0_CLKFBOUT_BUF false
C_MMCM0_CLOCK_HOLD false
C_MMCM0_STARTUP_WAIT false
C_MMCM0_EXT_RESET_HIGH 1
C_MMCM0_FAMILY virtex6
C_MMCM0_CLKOUT0_BUF false
C_MMCM0_CLKOUT1_BUF false
C_MMCM0_CLKOUT2_BUF false
C_MMCM0_CLKOUT3_BUF false
C_MMCM0_CLKOUT4_BUF false
C_MMCM0_CLKOUT5_BUF false
C_MMCM0_CLKOUT6_BUF false
C_MMCM0_CLKIN1_MODULE NONE
C_MMCM0_CLKIN1_PORT NONE
C_MMCM0_CLKFBIN_MODULE NONE
C_MMCM0_CLKFBIN_PORT NONE
C_MMCM0_RST_MODULE NONE
C_MMCM1_BANDWIDTH OPTIMIZED
C_MMCM1_CLKFBOUT_MULT_F 1.000000
C_MMCM1_CLKFBOUT_PHASE 0.000000
C_MMCM1_CLKFBOUT_USE_FINE_PS false
C_MMCM1_CLKIN1_PERIOD 0.000000
C_MMCM1_CLKOUT0_DIVIDE_F 1.000000
C_MMCM1_CLKOUT0_DUTY_CYCLE 0.500000
C_MMCM1_CLKOUT0_PHASE 0.000000
C_MMCM1_CLKOUT1_DIVIDE 1
C_MMCM1_CLKOUT1_DUTY_CYCLE 0.500000
C_MMCM1_CLKOUT1_PHASE 0.000000
C_MMCM1_CLKOUT2_DIVIDE 1
C_MMCM1_CLKOUT2_DUTY_CYCLE 0.500000
C_MMCM1_CLKOUT2_PHASE 0.000000
C_MMCM1_CLKOUT3_DIVIDE 1
C_MMCM1_CLKOUT3_DUTY_CYCLE 0.500000
C_MMCM1_CLKOUT3_PHASE 0.000000
C_MMCM1_CLKOUT4_DIVIDE 1
C_MMCM1_CLKOUT4_DUTY_CYCLE 0.500000
C_MMCM1_CLKOUT4_PHASE 0.000000
C_MMCM1_CLKOUT4_CASCADE false
C_MMCM1_CLKOUT5_DIVIDE 1
C_MMCM1_CLKOUT5_DUTY_CYCLE 0.500000
C_MMCM1_CLKOUT5_PHASE 0.000000
C_MMCM1_CLKOUT6_DIVIDE 1
C_MMCM1_CLKOUT6_DUTY_CYCLE 0.500000
C_MMCM1_CLKOUT6_PHASE 0.000000
C_MMCM1_CLKOUT0_USE_FINE_PS false
C_MMCM1_CLKOUT1_USE_FINE_PS false
C_MMCM1_CLKOUT2_USE_FINE_PS false
C_MMCM1_CLKOUT3_USE_FINE_PS false
C_MMCM1_CLKOUT4_USE_FINE_PS false
C_MMCM1_CLKOUT5_USE_FINE_PS false
C_MMCM1_CLKOUT6_USE_FINE_PS false
C_MMCM1_COMPENSATION ZHOLD
C_MMCM1_DIVCLK_DIVIDE 1
C_MMCM1_REF_JITTER1 0.010000
C_MMCM1_CLKIN1_BUF false
C_MMCM1_CLKFBOUT_BUF false
C_MMCM1_CLOCK_HOLD false
C_MMCM1_STARTUP_WAIT false
C_MMCM1_EXT_RESET_HIGH 1
C_MMCM1_FAMILY virtex6
C_MMCM1_CLKOUT0_BUF false
C_MMCM1_CLKOUT1_BUF false
C_MMCM1_CLKOUT2_BUF false
C_MMCM1_CLKOUT3_BUF false
C_MMCM1_CLKOUT4_BUF false
C_MMCM1_CLKOUT5_BUF false
C_MMCM1_CLKOUT6_BUF false
C_MMCM1_CLKIN1_MODULE NONE
C_MMCM1_CLKIN1_PORT NONE
C_MMCM1_CLKFBIN_MODULE NONE
C_MMCM1_CLKFBIN_PORT NONE
C_MMCM1_RST_MODULE NONE
C_MMCM2_BANDWIDTH OPTIMIZED
C_MMCM2_CLKFBOUT_MULT_F 1.000000
C_MMCM2_CLKFBOUT_PHASE 0.000000
C_MMCM2_CLKFBOUT_USE_FINE_PS false
C_MMCM2_CLKIN1_PERIOD 0.000000
C_MMCM2_CLKOUT0_DIVIDE_F 1.000000
C_MMCM2_CLKOUT0_DUTY_CYCLE 0.500000
C_MMCM2_CLKOUT0_PHASE 0.000000
C_MMCM2_CLKOUT1_DIVIDE 1
C_MMCM2_CLKOUT1_DUTY_CYCLE 0.500000
C_MMCM2_CLKOUT1_PHASE 0.000000
C_MMCM2_CLKOUT2_DIVIDE 1
C_MMCM2_CLKOUT2_DUTY_CYCLE 0.500000
C_MMCM2_CLKOUT2_PHASE 0.000000
C_MMCM2_CLKOUT3_DIVIDE 1
C_MMCM2_CLKOUT3_DUTY_CYCLE 0.500000
C_MMCM2_CLKOUT3_PHASE 0.000000
C_MMCM2_CLKOUT4_DIVIDE 1
C_MMCM2_CLKOUT4_DUTY_CYCLE 0.500000
C_MMCM2_CLKOUT4_PHASE 0.000000
C_MMCM2_CLKOUT4_CASCADE false
C_MMCM2_CLKOUT5_DIVIDE 1
C_MMCM2_CLKOUT5_DUTY_CYCLE 0.500000
C_MMCM2_CLKOUT5_PHASE 0.000000
C_MMCM2_CLKOUT6_DIVIDE 1
C_MMCM2_CLKOUT6_DUTY_CYCLE 0.500000
C_MMCM2_CLKOUT6_PHASE 0.000000
C_MMCM2_CLKOUT0_USE_FINE_PS false
C_MMCM2_CLKOUT1_USE_FINE_PS false
C_MMCM2_CLKOUT2_USE_FINE_PS false
C_MMCM2_CLKOUT3_USE_FINE_PS false
C_MMCM2_CLKOUT4_USE_FINE_PS false
C_MMCM2_CLKOUT5_USE_FINE_PS false
C_MMCM2_CLKOUT6_USE_FINE_PS false
C_MMCM2_COMPENSATION ZHOLD
C_MMCM2_DIVCLK_DIVIDE 1
C_MMCM2_REF_JITTER1 0.010000
C_MMCM2_CLKIN1_BUF false
C_MMCM2_CLKFBOUT_BUF false
C_MMCM2_CLOCK_HOLD false
C_MMCM2_STARTUP_WAIT false
C_MMCM2_EXT_RESET_HIGH 1
C_MMCM2_FAMILY virtex6
C_MMCM2_CLKOUT0_BUF false
C_MMCM2_CLKOUT1_BUF false
C_MMCM2_CLKOUT2_BUF false
C_MMCM2_CLKOUT3_BUF false
C_MMCM2_CLKOUT4_BUF false
C_MMCM2_CLKOUT5_BUF false
C_MMCM2_CLKOUT6_BUF false
C_MMCM2_CLKIN1_MODULE NONE
C_MMCM2_CLKIN1_PORT NONE
C_MMCM2_CLKFBIN_MODULE NONE
C_MMCM2_CLKFBIN_PORT NONE
C_MMCM2_RST_MODULE NONE
C_MMCM3_BANDWIDTH OPTIMIZED
C_MMCM3_CLKFBOUT_MULT_F 1.000000
C_MMCM3_CLKFBOUT_PHASE 0.000000
C_MMCM3_CLKFBOUT_USE_FINE_PS false
C_MMCM3_CLKIN1_PERIOD 0.000000
C_MMCM3_CLKOUT0_DIVIDE_F 1.000000
C_MMCM3_CLKOUT0_DUTY_CYCLE 0.500000
C_MMCM3_CLKOUT0_PHASE 0.000000
C_MMCM3_CLKOUT1_DIVIDE 1
C_MMCM3_CLKOUT1_DUTY_CYCLE 0.500000
C_MMCM3_CLKOUT1_PHASE 0.000000
C_MMCM3_CLKOUT2_DIVIDE 1
C_MMCM3_CLKOUT2_DUTY_CYCLE 0.500000
C_MMCM3_CLKOUT2_PHASE 0.000000
C_MMCM3_CLKOUT3_DIVIDE 1
C_MMCM3_CLKOUT3_DUTY_CYCLE 0.500000
C_MMCM3_CLKOUT3_PHASE 0.000000
C_MMCM3_CLKOUT4_DIVIDE 1
C_MMCM3_CLKOUT4_DUTY_CYCLE 0.500000
C_MMCM3_CLKOUT4_PHASE 0.000000
C_MMCM3_CLKOUT4_CASCADE false
C_MMCM3_CLKOUT5_DIVIDE 1
C_MMCM3_CLKOUT5_DUTY_CYCLE 0.500000
C_MMCM3_CLKOUT5_PHASE 0.000000
C_MMCM3_CLKOUT6_DIVIDE 1
C_MMCM3_CLKOUT6_DUTY_CYCLE 0.500000
C_MMCM3_CLKOUT6_PHASE 0.000000
C_MMCM3_CLKOUT0_USE_FINE_PS false
C_MMCM3_CLKOUT1_USE_FINE_PS false
C_MMCM3_CLKOUT2_USE_FINE_PS false
C_MMCM3_CLKOUT3_USE_FINE_PS false
C_MMCM3_CLKOUT4_USE_FINE_PS false
C_MMCM3_CLKOUT5_USE_FINE_PS false
C_MMCM3_CLKOUT6_USE_FINE_PS false
C_MMCM3_COMPENSATION ZHOLD
C_MMCM3_DIVCLK_DIVIDE 1
C_MMCM3_REF_JITTER1 0.010000
C_MMCM3_CLKIN1_BUF false
C_MMCM3_CLKFBOUT_BUF false
C_MMCM3_CLOCK_HOLD false
C_MMCM3_STARTUP_WAIT false
C_MMCM3_EXT_RESET_HIGH 1
C_MMCM3_FAMILY virtex6
C_MMCM3_CLKOUT0_BUF false
C_MMCM3_CLKOUT1_BUF false
C_MMCM3_CLKOUT2_BUF false
C_MMCM3_CLKOUT3_BUF false
C_MMCM3_CLKOUT4_BUF false
C_MMCM3_CLKOUT5_BUF false
C_MMCM3_CLKOUT6_BUF false
C_MMCM3_CLKIN1_MODULE NONE
C_MMCM3_CLKIN1_PORT NONE
C_MMCM3_CLKFBIN_MODULE NONE
C_MMCM3_CLKFBIN_PORT NONE
C_MMCM3_RST_MODULE NONE
C_CLKIN_FREQ 50000000
C_CLKFBIN_FREQ 0
C_CLKFBIN_DESKEW NONE
C_PSDONE_GROUP NONE
C_CLKOUT0_FREQ 50000000
C_CLKOUT0_PHASE 0
C_CLKOUT0_GROUP NONE
C_CLKOUT0_BUF TRUE
C_CLKOUT0_VARIABLE_PHASE FALSE
C_CLKOUT1_FREQ 0
C_CLKOUT1_PHASE 0
C_CLKOUT1_GROUP NONE
C_CLKOUT1_BUF TRUE
C_CLKOUT1_VARIABLE_PHASE FALSE
C_CLKOUT2_FREQ 0
C_CLKOUT2_PHASE 0
C_CLKOUT2_GROUP NONE
C_CLKOUT2_BUF TRUE
C_CLKOUT2_VARIABLE_PHASE FALSE
C_CLKOUT3_FREQ 0
C_CLKOUT3_PHASE 0
C_CLKOUT3_GROUP NONE
C_CLKOUT3_BUF TRUE
C_CLKOUT3_VARIABLE_PHASE FALSE
C_CLKOUT4_FREQ 0
C_CLKOUT4_PHASE 0
C_CLKOUT4_GROUP NONE
C_CLKOUT4_BUF TRUE
C_CLKOUT4_VARIABLE_PHASE FALSE
C_CLKOUT5_FREQ 0
C_CLKOUT5_PHASE 0
C_CLKOUT5_GROUP NONE
C_CLKOUT5_BUF TRUE
C_CLKOUT5_VARIABLE_PHASE FALSE
C_CLKOUT6_FREQ 0
C_CLKOUT6_PHASE 0
C_CLKOUT6_GROUP NONE
C_CLKOUT6_BUF TRUE
C_CLKOUT6_VARIABLE_PHASE FALSE
C_CLKOUT7_FREQ 0
C_CLKOUT7_PHASE 0
C_CLKOUT7_GROUP NONE
C_CLKOUT7_BUF TRUE
C_CLKOUT7_VARIABLE_PHASE FALSE
C_CLKOUT8_FREQ 0
C_CLKOUT8_PHASE 0
C_CLKOUT8_GROUP NONE
C_CLKOUT8_BUF TRUE
C_CLKOUT8_VARIABLE_PHASE FALSE
C_CLKOUT9_FREQ 0
C_CLKOUT9_PHASE 0
C_CLKOUT9_GROUP NONE
C_CLKOUT9_BUF TRUE
C_CLKOUT9_VARIABLE_PHASE FALSE
C_CLKOUT10_FREQ 0
C_CLKOUT10_PHASE 0
C_CLKOUT10_GROUP NONE
C_CLKOUT10_BUF TRUE
C_CLKOUT10_VARIABLE_PHASE FALSE
C_CLKOUT11_FREQ 0
C_CLKOUT11_PHASE 0
C_CLKOUT11_GROUP NONE
C_CLKOUT11_BUF TRUE
C_CLKOUT11_VARIABLE_PHASE FALSE
C_CLKOUT12_FREQ 0
C_CLKOUT12_PHASE 0
C_CLKOUT12_GROUP NONE
C_CLKOUT12_BUF TRUE
C_CLKOUT12_VARIABLE_PHASE FALSE
C_CLKOUT13_FREQ 0
C_CLKOUT13_PHASE 0
C_CLKOUT13_GROUP NONE
C_CLKOUT13_BUF TRUE
C_CLKOUT13_VARIABLE_PHASE FALSE
C_CLKOUT14_FREQ 0
C_CLKOUT14_PHASE 0
C_CLKOUT14_GROUP NONE
C_CLKOUT14_BUF TRUE
C_CLKOUT14_VARIABLE_PHASE FALSE
C_CLKOUT15_FREQ 0
C_CLKOUT15_PHASE 0
C_CLKOUT15_GROUP NONE
C_CLKOUT15_BUF TRUE
C_CLKOUT15_VARIABLE_PHASE FALSE
C_CLKFBOUT_FREQ 0
C_CLKFBOUT_PHASE 0
C_CLKFBOUT_GROUP NONE
C_CLKFBOUT_BUF TRUE
 
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.


proc_sys_reset_0   Processor System Reset Module
Reset management module

IP Specs
Core Version Documentation
proc_sys_reset 2.00.a IP


proc_sys_reset_0 IP Image
PORT LIST
These are the ports listed in the MHS file. Please refer to the IP documentation for complete information about module ports.
# NAME DIR [LSB:MSB] SIGNAL
0 Slowest_sync_clk I 1 clk_50_0000MHz
1 Ext_Reset_In I 1 sys_rst_s
2 MB_Debug_Sys_Rst I 1 Debug_SYS_Rst
3 Dcm_locked I 1 Dcm_all_locked
4 MB_Reset O 1 mb_reset
5 Bus_Struct_Reset O 1 sys_bus_reset
6 Peripheral_Reset O 1 sys_periph_reset


Parameters
These are the current parameter settings for this module.
Please refer to the IP documentation for complete information about module parameters.
Parameters marked with yellow indicate parameters set by the user.
Parameters marked with blue indicate parameters set by the system.
Name Value
C_SUBFAMILY lx
C_EXT_RST_WIDTH 4
C_AUX_RST_WIDTH 4
C_EXT_RESET_HIGH 1
C_AUX_RESET_HIGH 1
C_NUM_BUS_RST 1
C_NUM_PERP_RST 1
C_FAMILY virtex5
Post Synthesis Device Utilization
Device utilization information is not available for this IP. Run platgen to generate synthesis information.




Timing Information TOC


Post Synthesis Clock Limits
No clocks could be identified in the design. Run platgen to generate synthesis information.