Name |
Value |
C_MMCM0_CLKOUT4_CASCADE |
false |
C_MMCM0_CLKOUT5_DIVIDE |
1 |
C_MMCM0_CLKOUT5_DUTY_CYCLE |
0.500000 |
C_MMCM0_CLKOUT5_PHASE |
0.000000 |
C_MMCM0_CLKOUT6_DIVIDE |
1 |
C_MMCM0_CLKOUT6_DUTY_CYCLE |
0.500000 |
C_MMCM0_CLKOUT6_PHASE |
0.000000 |
C_MMCM0_CLKOUT0_USE_FINE_PS |
false |
C_MMCM0_CLKOUT1_USE_FINE_PS |
false |
C_MMCM0_CLKOUT2_USE_FINE_PS |
false |
C_MMCM0_CLKOUT3_USE_FINE_PS |
false |
C_MMCM0_CLKOUT4_USE_FINE_PS |
false |
C_MMCM0_CLKOUT5_USE_FINE_PS |
false |
C_MMCM0_CLKOUT6_USE_FINE_PS |
false |
C_MMCM0_COMPENSATION |
ZHOLD |
C_MMCM0_DIVCLK_DIVIDE |
1 |
C_MMCM0_REF_JITTER1 |
0.010000 |
C_MMCM0_CLKIN1_BUF |
false |
C_MMCM0_CLKFBOUT_BUF |
false |
C_MMCM0_CLOCK_HOLD |
false |
C_MMCM0_STARTUP_WAIT |
false |
C_MMCM0_EXT_RESET_HIGH |
1 |
C_MMCM0_FAMILY |
virtex6 |
C_MMCM0_CLKOUT0_BUF |
false |
C_MMCM0_CLKOUT1_BUF |
false |
C_MMCM0_CLKOUT2_BUF |
false |
C_MMCM0_CLKOUT3_BUF |
false |
C_MMCM0_CLKOUT4_BUF |
false |
C_MMCM0_CLKOUT5_BUF |
false |
C_MMCM0_CLKOUT6_BUF |
false |
C_MMCM0_CLKIN1_MODULE |
NONE |
C_MMCM0_CLKIN1_PORT |
NONE |
C_MMCM0_CLKFBIN_MODULE |
NONE |
C_MMCM0_CLKFBIN_PORT |
NONE |
C_MMCM0_RST_MODULE |
NONE |
C_MMCM1_BANDWIDTH |
OPTIMIZED |
C_MMCM1_CLKFBOUT_MULT_F |
1.000000 |
C_MMCM1_CLKFBOUT_PHASE |
0.000000 |
C_MMCM1_CLKFBOUT_USE_FINE_PS |
false |
C_MMCM1_CLKIN1_PERIOD |
0.000000 |
C_MMCM1_CLKOUT0_DIVIDE_F |
1.000000 |
C_MMCM1_CLKOUT0_DUTY_CYCLE |
0.500000 |
C_MMCM1_CLKOUT0_PHASE |
0.000000 |
C_MMCM1_CLKOUT1_DIVIDE |
1 |
C_MMCM1_CLKOUT1_DUTY_CYCLE |
0.500000 |
C_MMCM1_CLKOUT1_PHASE |
0.000000 |
C_MMCM1_CLKOUT2_DIVIDE |
1 |
C_MMCM1_CLKOUT2_DUTY_CYCLE |
0.500000 |
C_MMCM1_CLKOUT2_PHASE |
0.000000 |
C_MMCM1_CLKOUT3_DIVIDE |
1 |
C_MMCM1_CLKOUT3_DUTY_CYCLE |
0.500000 |
C_MMCM1_CLKOUT3_PHASE |
0.000000 |
C_MMCM1_CLKOUT4_DIVIDE |
1 |
C_MMCM1_CLKOUT4_DUTY_CYCLE |
0.500000 |
C_MMCM1_CLKOUT4_PHASE |
0.000000 |
C_MMCM1_CLKOUT4_CASCADE |
false |
C_MMCM1_CLKOUT5_DIVIDE |
1 |
C_MMCM1_CLKOUT5_DUTY_CYCLE |
0.500000 |
C_MMCM1_CLKOUT5_PHASE |
0.000000 |
C_MMCM1_CLKOUT6_DIVIDE |
1 |
C_MMCM1_CLKOUT6_DUTY_CYCLE |
0.500000 |
C_MMCM1_CLKOUT6_PHASE |
0.000000 |
C_MMCM1_CLKOUT0_USE_FINE_PS |
false |
C_MMCM1_CLKOUT1_USE_FINE_PS |
false |
C_MMCM1_CLKOUT2_USE_FINE_PS |
false |
C_MMCM1_CLKOUT3_USE_FINE_PS |
false |
C_MMCM1_CLKOUT4_USE_FINE_PS |
false |
C_MMCM1_CLKOUT5_USE_FINE_PS |
false |
C_MMCM1_CLKOUT6_USE_FINE_PS |
false |
C_MMCM1_COMPENSATION |
ZHOLD |
C_MMCM1_DIVCLK_DIVIDE |
1 |
C_MMCM1_REF_JITTER1 |
0.010000 |
C_MMCM1_CLKIN1_BUF |
false |
C_MMCM1_CLKFBOUT_BUF |
false |
C_MMCM1_CLOCK_HOLD |
false |
C_MMCM1_STARTUP_WAIT |
false |
C_MMCM1_EXT_RESET_HIGH |
1 |
C_MMCM1_FAMILY |
virtex6 |
C_MMCM1_CLKOUT0_BUF |
false |
C_MMCM1_CLKOUT1_BUF |
false |
C_MMCM1_CLKOUT2_BUF |
false |
C_MMCM1_CLKOUT3_BUF |
false |
C_MMCM1_CLKOUT4_BUF |
false |
C_MMCM1_CLKOUT5_BUF |
false |
C_MMCM1_CLKOUT6_BUF |
false |
C_MMCM1_CLKIN1_MODULE |
NONE |
C_MMCM1_CLKIN1_PORT |
NONE |
C_MMCM1_CLKFBIN_MODULE |
NONE |
C_MMCM1_CLKFBIN_PORT |
NONE |
C_MMCM1_RST_MODULE |
NONE |
C_MMCM2_BANDWIDTH |
OPTIMIZED |
C_MMCM2_CLKFBOUT_MULT_F |
1.000000 |
C_MMCM2_CLKFBOUT_PHASE |
0.000000 |
C_MMCM2_CLKFBOUT_USE_FINE_PS |
false |
C_MMCM2_CLKIN1_PERIOD |
0.000000 |
C_MMCM2_CLKOUT0_DIVIDE_F |
1.000000 |
C_MMCM2_CLKOUT0_DUTY_CYCLE |
0.500000 |
C_MMCM2_CLKOUT0_PHASE |
0.000000 |
C_MMCM2_CLKOUT1_DIVIDE |
1 |
C_MMCM2_CLKOUT1_DUTY_CYCLE |
0.500000 |
C_MMCM2_CLKOUT1_PHASE |
0.000000 |
C_MMCM2_CLKOUT2_DIVIDE |
1 |
C_MMCM2_CLKOUT2_DUTY_CYCLE |
0.500000 |
C_MMCM2_CLKOUT2_PHASE |
0.000000 |
C_MMCM2_CLKOUT3_DIVIDE |
1 |
C_MMCM2_CLKOUT3_DUTY_CYCLE |
0.500000 |
C_MMCM2_CLKOUT3_PHASE |
0.000000 |
C_MMCM2_CLKOUT4_DIVIDE |
1 |
C_MMCM2_CLKOUT4_DUTY_CYCLE |
0.500000 |
C_MMCM2_CLKOUT4_PHASE |
0.000000 |
C_MMCM2_CLKOUT4_CASCADE |
false |
C_MMCM2_CLKOUT5_DIVIDE |
1 |
C_MMCM2_CLKOUT5_DUTY_CYCLE |
0.500000 |
C_MMCM2_CLKOUT5_PHASE |
0.000000 |
C_MMCM2_CLKOUT6_DIVIDE |
1 |
C_MMCM2_CLKOUT6_DUTY_CYCLE |
0.500000 |
C_MMCM2_CLKOUT6_PHASE |
0.000000 |
C_MMCM2_CLKOUT0_USE_FINE_PS |
false |
C_MMCM2_CLKOUT1_USE_FINE_PS |
false |
C_MMCM2_CLKOUT2_USE_FINE_PS |
false |
C_MMCM2_CLKOUT3_USE_FINE_PS |
false |
C_MMCM2_CLKOUT4_USE_FINE_PS |
false |
C_MMCM2_CLKOUT5_USE_FINE_PS |
false |
C_MMCM2_CLKOUT6_USE_FINE_PS |
false |
C_MMCM2_COMPENSATION |
ZHOLD |
C_MMCM2_DIVCLK_DIVIDE |
1 |
C_MMCM2_REF_JITTER1 |
0.010000 |
C_MMCM2_CLKIN1_BUF |
false |
C_MMCM2_CLKFBOUT_BUF |
false |
C_MMCM2_CLOCK_HOLD |
false |
C_MMCM2_STARTUP_WAIT |
false |
C_MMCM2_EXT_RESET_HIGH |
1 |
C_MMCM2_FAMILY |
virtex6 |
C_MMCM2_CLKOUT0_BUF |
false |
C_MMCM2_CLKOUT1_BUF |
false |
C_MMCM2_CLKOUT2_BUF |
false |
C_MMCM2_CLKOUT3_BUF |
false |
C_MMCM2_CLKOUT4_BUF |
false |
C_MMCM2_CLKOUT5_BUF |
false |
C_MMCM2_CLKOUT6_BUF |
false |
C_MMCM2_CLKIN1_MODULE |
NONE |
C_MMCM2_CLKIN1_PORT |
NONE |
C_MMCM2_CLKFBIN_MODULE |
NONE |
C_MMCM2_CLKFBIN_PORT |
NONE |
C_MMCM2_RST_MODULE |
NONE |
C_MMCM3_BANDWIDTH |
OPTIMIZED |
C_MMCM3_CLKFBOUT_MULT_F |
1.000000 |
C_MMCM3_CLKFBOUT_PHASE |
0.000000 |
C_MMCM3_CLKFBOUT_USE_FINE_PS |
false |
C_MMCM3_CLKIN1_PERIOD |
0.000000 |
C_MMCM3_CLKOUT0_DIVIDE_F |
1.000000 |
C_MMCM3_CLKOUT0_DUTY_CYCLE |
0.500000 |
C_MMCM3_CLKOUT0_PHASE |
0.000000 |
C_MMCM3_CLKOUT1_DIVIDE |
1 |
C_MMCM3_CLKOUT1_DUTY_CYCLE |
0.500000 |
C_MMCM3_CLKOUT1_PHASE |
0.000000 |
C_MMCM3_CLKOUT2_DIVIDE |
1 |
C_MMCM3_CLKOUT2_DUTY_CYCLE |
0.500000 |
C_MMCM3_CLKOUT2_PHASE |
0.000000 |
C_MMCM3_CLKOUT3_DIVIDE |
1 |
C_MMCM3_CLKOUT3_DUTY_CYCLE |
0.500000 |
C_MMCM3_CLKOUT3_PHASE |
0.000000 |
C_MMCM3_CLKOUT4_DIVIDE |
1 |
C_MMCM3_CLKOUT4_DUTY_CYCLE |
0.500000 |
C_MMCM3_CLKOUT4_PHASE |
0.000000 |
C_MMCM3_CLKOUT4_CASCADE |
false |
C_MMCM3_CLKOUT5_DIVIDE |
1 |
C_MMCM3_CLKOUT5_DUTY_CYCLE |
0.500000 |
C_MMCM3_CLKOUT5_PHASE |
0.000000 |
C_MMCM3_CLKOUT6_DIVIDE |
1 |
C_MMCM3_CLKOUT6_DUTY_CYCLE |
0.500000 |
C_MMCM3_CLKOUT6_PHASE |
0.000000 |
C_MMCM3_CLKOUT0_USE_FINE_PS |
false |
C_MMCM3_CLKOUT1_USE_FINE_PS |
false |
C_MMCM3_CLKOUT2_USE_FINE_PS |
false |
C_MMCM3_CLKOUT3_USE_FINE_PS |
false |
C_MMCM3_CLKOUT4_USE_FINE_PS |
false |
C_MMCM3_CLKOUT5_USE_FINE_PS |
false |
C_MMCM3_CLKOUT6_USE_FINE_PS |
false |
C_MMCM3_COMPENSATION |
ZHOLD |
C_MMCM3_DIVCLK_DIVIDE |
1 |
C_MMCM3_REF_JITTER1 |
0.010000 |
C_MMCM3_CLKIN1_BUF |
false |
C_MMCM3_CLKFBOUT_BUF |
false |
C_MMCM3_CLOCK_HOLD |
false |
C_MMCM3_STARTUP_WAIT |
false |
C_MMCM3_EXT_RESET_HIGH |
1 |
C_MMCM3_FAMILY |
virtex6 |
C_MMCM3_CLKOUT0_BUF |
false |
C_MMCM3_CLKOUT1_BUF |
false |
C_MMCM3_CLKOUT2_BUF |
false |
C_MMCM3_CLKOUT3_BUF |
false |
C_MMCM3_CLKOUT4_BUF |
false |
C_MMCM3_CLKOUT5_BUF |
false |
C_MMCM3_CLKOUT6_BUF |
false |
C_MMCM3_CLKIN1_MODULE |
NONE |
C_MMCM3_CLKIN1_PORT |
NONE |
C_MMCM3_CLKFBIN_MODULE |
NONE |
C_MMCM3_CLKFBIN_PORT |
NONE |
C_MMCM3_RST_MODULE |
NONE |
C_CLKIN_FREQ |
50000000 |
C_CLKFBIN_FREQ |
0 |
C_CLKFBIN_DESKEW |
NONE |
C_PSDONE_GROUP |
NONE |
C_CLKOUT0_FREQ |
50000000 |
C_CLKOUT0_PHASE |
0 |
C_CLKOUT0_GROUP |
NONE |
C_CLKOUT0_BUF |
TRUE |
C_CLKOUT0_VARIABLE_PHASE |
FALSE |
C_CLKOUT1_FREQ |
0 |
C_CLKOUT1_PHASE |
0 |
C_CLKOUT1_GROUP |
NONE |
C_CLKOUT1_BUF |
TRUE |
C_CLKOUT1_VARIABLE_PHASE |
FALSE |
C_CLKOUT2_FREQ |
0 |
C_CLKOUT2_PHASE |
0 |
C_CLKOUT2_GROUP |
NONE |
C_CLKOUT2_BUF |
TRUE |
C_CLKOUT2_VARIABLE_PHASE |
FALSE |
C_CLKOUT3_FREQ |
0 |
C_CLKOUT3_PHASE |
0 |
C_CLKOUT3_GROUP |
NONE |
C_CLKOUT3_BUF |
TRUE |
C_CLKOUT3_VARIABLE_PHASE |
FALSE |
C_CLKOUT4_FREQ |
0 |
C_CLKOUT4_PHASE |
0 |
C_CLKOUT4_GROUP |
NONE |
C_CLKOUT4_BUF |
TRUE |
C_CLKOUT4_VARIABLE_PHASE |
FALSE |
C_CLKOUT5_FREQ |
0 |
C_CLKOUT5_PHASE |
0 |
C_CLKOUT5_GROUP |
NONE |
C_CLKOUT5_BUF |
TRUE |
C_CLKOUT5_VARIABLE_PHASE |
FALSE |
C_CLKOUT6_FREQ |
0 |
C_CLKOUT6_PHASE |
0 |
C_CLKOUT6_GROUP |
NONE |
C_CLKOUT6_BUF |
TRUE |
C_CLKOUT6_VARIABLE_PHASE |
FALSE |
C_CLKOUT7_FREQ |
0 |
C_CLKOUT7_PHASE |
0 |
C_CLKOUT7_GROUP |
NONE |
C_CLKOUT7_BUF |
TRUE |
C_CLKOUT7_VARIABLE_PHASE |
FALSE |
C_CLKOUT8_FREQ |
0 |
C_CLKOUT8_PHASE |
0 |
C_CLKOUT8_GROUP |
NONE |
C_CLKOUT8_BUF |
TRUE |
C_CLKOUT8_VARIABLE_PHASE |
FALSE |
C_CLKOUT9_FREQ |
0 |
C_CLKOUT9_PHASE |
0 |
C_CLKOUT9_GROUP |
NONE |
C_CLKOUT9_BUF |
TRUE |
C_CLKOUT9_VARIABLE_PHASE |
FALSE |
C_CLKOUT10_FREQ |
0 |
C_CLKOUT10_PHASE |
0 |
C_CLKOUT10_GROUP |
NONE |
C_CLKOUT10_BUF |
TRUE |
C_CLKOUT10_VARIABLE_PHASE |
FALSE |
C_CLKOUT11_FREQ |
0 |
C_CLKOUT11_PHASE |
0 |
C_CLKOUT11_GROUP |
NONE |
C_CLKOUT11_BUF |
TRUE |
C_CLKOUT11_VARIABLE_PHASE |
FALSE |
C_CLKOUT12_FREQ |
0 |
C_CLKOUT12_PHASE |
0 |
C_CLKOUT12_GROUP |
NONE |
C_CLKOUT12_BUF |
TRUE |
C_CLKOUT12_VARIABLE_PHASE |
FALSE |
C_CLKOUT13_FREQ |
0 |
C_CLKOUT13_PHASE |
0 |
C_CLKOUT13_GROUP |
NONE |
C_CLKOUT13_BUF |
TRUE |
C_CLKOUT13_VARIABLE_PHASE |
FALSE |
C_CLKOUT14_FREQ |
0 |
C_CLKOUT14_PHASE |
0 |
C_CLKOUT14_GROUP |
NONE |
C_CLKOUT14_BUF |
TRUE |
C_CLKOUT14_VARIABLE_PHASE |
FALSE |
C_CLKOUT15_FREQ |
0 |
C_CLKOUT15_PHASE |
0 |
C_CLKOUT15_GROUP |
NONE |
C_CLKOUT15_BUF |
TRUE |
C_CLKOUT15_VARIABLE_PHASE |
FALSE |
C_CLKFBOUT_FREQ |
0 |
C_CLKFBOUT_PHASE |
0 |
C_CLKFBOUT_GROUP |
NONE |
C_CLKFBOUT_BUF |
TRUE |
|