Nexys 4 DDR - Getting Started with Microblaze Servers
Warning! This guide is out of date. While it should still work as written in the original versions of the tools it was written for, users have reported that resulting designs are not functional in recent versions - 2022.2 being the latest at time of writing.
Overview
This guide will provide a step by step walk-through of creating a Microblaze based hardware design using the Vivado IP Integrator that will build over the Getting Started with Microblaze guide by making use of the on-board Ethernet port and GPIOs for the Nexys 4 DDR FPGA board.
At the end of this tutorial you will have a comprehensive hardware design for Nexys4 DDR that makes use of various Hardware ports on the Nexys 4 DDR which are managed by the Microblaze Softcore Processor block.
Prerequisites
Hardware
- Digilent Nexys 4 DDR FPGA Board
- Micro USB Cable
Software
- Xilinx Vivado 2015.X with the SDK package
Board Support Files
- Board Support Files
- These files will describe GPIO interfaces on your board and make it easier to select your FPGA board and add GPIO IP blocks.
- Follow this Wiki guide (Vivado Board Files for Digilent 7-Series FPGA Boards) on how to install Board Support Files for Vivado.
Important!
Xilinx deprecated the Ethernet PHY MII to Reduced MII (MII2RMII) after Vivado version 2019.1 without a direct replacement. This core can still potentially be used in newer versions by obtaining a copy of the IP's sources from an installation of Vivado 2019.1 or earlier. You can include it in 2019.2 onwards by including the IP sources as you would a regular IP repository. This thread, from the Xilinx support forum, has additional information on the workaround.
Introduction
Microblaze is a soft IP core from Xilinx that will implement a microprocessor entirely within the Xilinx FPGA general purpose memory and logic fabric. For this tutorial, we are going to add Ethernet functionality and create an echo server.
General Design Flow
I. Vivado
- Open Vivado and select Nexys 4 DDR board
- Create an new Vivado Project
- Create empty block design workspace inside the new project
- Add required IP blocks using the IP integrator tool and build Hardware Design
- Validate and save block design
- Create HDL system wrapper
- Run design Synthesis and Implementation
- Generate Bit File
- Export Hardware Design including the generated bit stream file to SDK tool
- Launch SDK
Now the Hardware design is exported to the SDK tool. The Vivado to SDK hand-off is done internally through Vivado. We will use SDK to create a Software application that will use the customized board interface data and FPGA hardware configuration by importing the hardware design information from Vivado.
II. SDK
- Create new application project and select default Hello World template
- Program FPGA
- Run configuration by selecting the correct UART COM Port and Baud Rate
Tutorial
1. Creating a New Project
1.4) If you have followed the Board Support File Wiki guide then click next and select Boards. From the filter options make required selections for Vendor, Display Name and Board Revision. Nexys 4 DDR should be displayed in the selection list. A mismatch in selecting the correct board name will cause errors.
At this point you have successfully created a project that will properly communicate with the Nexys 4 DDR.
2. Creating New Block Design
2.1) This is the main project window where you can create a IP based block design or add RTL based design sources. The flow navigator panel on the left provides multiple options on how to create a hardware design, perform simulation, run synthesis and implementation and generate a bit file. You can also program the board directly from Vivado with the generated bit file for an RTL project using the Hardware Manager. For our design, we will use the IP Integrator to create a new block design.
Add the Microblaze Core:
2.4) This is the Xilinx Microblaze IP block. When a new IP block is added the user can customize the block properties by either clicking on the Run Block Automation message prompt or by double clicking on the block itself.
2.5) Select Run Block Automation and a customization assistant window will open with default settings. Set up like picture below.
Adding the Necessary Output Clocks:
3. Adding the IP Cores
3.1) We will now add all of the necessary IP blocks to our project. There are 4 cores we will add:* Memory Interface Generator * Ethernet PHY MII to Reduced MII * AXI Uartlite * AXI EthernetLite * AXI Timer
4. Configuring and Routing the IP Cores
4.1) Click Run Block Automation and run it for the mig_7series_0 block.
When the MIG block automation is run, you will see this specific error message [BD 41-1273]. You can ignore this for now. It will not affect your design in any way. The MIG block will be configured as per the board support files that have been downloaded for the Nexys 4 DDR. Click OK to dismiss this message.
4.14) Open your new constraints file and paste the following line of code in it:
set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; # Sch=eth_ref_clkSave the xdc file when you are finished.
5. Exporting Hardware Design to SDK
5.1) On the top left corner of the window, from the tool bar click on File→Export Hardware. Make sure the generated bitstream is included by checking the box. This will export the hardware design with system wrapper for the Software Development Tool - Vivado SDK.
There is currently a bug where the download.bit file is not generated for the Nexys 4 DDR board. To work around this, click File→Export→Export Bitstream File… then navigate to project/project.sdk/design_1_wrapper_hw_platform_0 and export a new bit file called “download”
6. Launching SDK
7. Inside SDK for Vivado
7.1) A new window for SDK will open. The HW design specification and included IP blocks are displayed in the system.hdf file. SDK tool is independent of Vivado, i.e. from this point, you can create your SW project in C/C++ on top of the exported HW design. If necessary, you can also launch SDK directly from the SDK folder created in the main Vivado Project directory.
Now, if you need to go back to Vivado and make changes to the HW design, then it is recommended to close the SDK window and make the required HW design edits in Vivado. After this you must follow the sequence of creating a new HDL wrapper, save design and bit file generation. This new bit file and system wrapper must then be exported to SDK.
Since we do not have any HW design edits at this point, we will proceed with creating a software application to run an echo server.
8. Creating New Application Project in SDK
8.1) Go to File→New→Application Project in the main toolbar. A new project window will pop up. Give your SDK project a name that has no empty spaces as shown below. Make sure the Target Hardware is the correct hardware design. In our case, it will be design_1_wrapper_hw_platform_0.
If for example, you also have another hardware design in the Project Explorer window, then you will also see this design name in the Target Hardware drop down selection list.
Since we only have one hardware design design_1_wrapper_hw_platform_0 this will be our target hardware. Select Create New under Board Support Package. The tool will automatically populate the Board Support Package name to match with the give project name. Click Next.
8.3) After completing the previous step, you will see two new folders in the Project Explorer panel. echo_server which contains all the binaries, .C and .H (Header) files, and echo_server_bsp which is the board support folder.
echo_server is our main working source folder. This also contains an important file shown here in the src folder called lscript.ld. This is a Xilinx auto generated linker script file. Double click on this file to open.
9. Verify Linker Script File for Memory Region Mapping
9.1) In the linker script, take a look at the Section to Memory Region Mapping box. If you did the Make DDR2 External step then the target memory region column must read mig_7series_0.
10. Setting PHY Link Speed
10.2) Once in Board Support Package Settings select Overview→standalone→lwip141. The configuration table for the lwip141 library should now be visible on the right. Navigate to temac_adapter_options→phy_link_speed. Here you will need to change CONFIG_LINKSPEED_AUTODETECT to CONFIG_LINKSPEED100 so that it looks like the picture below.
11. Programming FPGA with Bit File
11.1) Make sure that the Nexys 4 DDR is turned on and connected to the host PC via micro USB cable. On the main toolbar, click Xilinx Tools→Program FPGA
Make sure that the Hardware Platform is selected as design_1_wrapper_hw_platform_0.
In the software configuration box, under ELF File to Initialize in Block RAM column, the row option must read bootloop. If not, click on the row and select bootloop.
Now click on Program.
12. Setting up the SDK Serial Console and Running the Server
13. Running the Server
14. Testing the Server with Tera Term
14.1) Connect your PC to your Nexys 4 DDR using an Ethernet cable. If using a router, watch the UART console to find out the IP of the Nexys 4 DDR echo server, and connect to that IP address. Setting up the connection as static is unnecessary.
14.2) In order to connect to the echo server directly from your computer, you must set up your Ethernet connection with a static IP address. To do this:
14.2.5) Click the Use the following IP address: bullet and type in an IP address “192.168.1.XX”, where XX is a value between 2 and 255, but not 10. This IP must not be the same as another already on your network. Make sure to click within the Subnet mask field to get the 255.255.255.0 mask to autofill. Click Ok and you will have a static IP address.